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公开(公告)号：US20050104133A1
公开(公告)日：2005-05-19
申请号：US10921854
申请日：2004-08-20
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： H01L21/822 , G11C5/06 , G11C11/417 , H01L21/82 , H01L27/02 , H01L27/04 , H01L27/092 , H01L27/118 , H03K3/037 , H03K3/356 , H03K3/3562 , H03K19/00 , H03K19/0175 , H03K19/08 , H01L29/76 , G11C11/24
CPC分类号： G01R31/318572 , G11C5/063 , G11C11/417 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2924/0002 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H01L2924/00
摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.
摘要翻译： 在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。 虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。 用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。 优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。 为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。 电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。
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公开(公告)号：US20050007183A1
公开(公告)日：2005-01-13
申请号：US10911664
申请日：2004-08-05
IPC分类号： H03K3/01 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00323 , H03K19/00384 , H03K19/018585
摘要： A semiconductor integrated circuit device includes a logic circuit to perform a predetermined process, a clock generator to supply a clock signal to the logic circuit, and a speed controller to control the operation speed of the logic circuit. The clock generator changes the frequency of the clock signal by a frequency control signal during a time when the logic circuit is operating, and the speed controller controls the operating speed of the logic circuit in accordance with a change in the clock signal.
摘要翻译： 半导体集成电路器件包括执行预定处理的逻辑电路，向逻辑电路提供时钟信号的时钟发生器以及控制逻辑电路的操作速度的速度控制器。 在逻辑电路工作时，时钟发生器通过频率控制信号来改变时钟信号的频率，速度控制器根据时钟信号的变化来控制逻辑电路的工作速度。
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公开(公告)号：US06819158B2
公开(公告)日：2004-11-16
申请号：US10446797
申请日：2003-05-29
IPC分类号： H03H1126
CPC分类号： H03K19/018585 , H03K19/00384
摘要： A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit is correspondent to the frequency of the reference clock signal.
摘要翻译： 半导体集成电路包括由p沟道MIS晶体管和n沟道MIS晶体管形成的逻辑电路，由p沟道MIS晶体管和n沟道MIS晶体管形成的可变振荡频率的第一振荡电路，控制 产生用于控制p沟道和n沟道MIS晶体管的阈值电压的控制信号的电路，以及根据操作模式产生不同频率的多个参考时钟信号的第二振荡电路。 控制电路接收参考时钟信号并用控制信号控制第一振荡电路，使得第一振荡电路的振荡频率对应于参考时钟信号的频率。
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公开(公告)号：US06720815B2
公开(公告)日：2004-04-13
申请号：US10105362
申请日：2002-03-26
申请人： Hiroyuki Mizuno
发明人： Hiroyuki Mizuno
IPC分类号： H03K300
摘要： In semiconductor integrated circuit devices containing a macro, a skew occurs between the clock pulse supplied to the latch in that mother circuit and the clock pulse supplied to the latch inside the macro. These clock skews obstruct the high frequency operation of the semiconductor integrated circuit device clock frequency so the semiconductor integrated circuit device cannot be operated at high speed. In a semiconductor integrated circuit device having a first clock processor means to generate a third clock pulse so a first clock pulse and a second clock pulse are input at an identical phase and identical frequency, a second clock processor means to generate a fifth clock pulse so that a third and a fourth clock pulse are input at an identical phase and identical frequency, and a first latch group and a second latch group comprised of a plurality of latches, and in this semiconductor integrated circuit device the second clock pulse is generated by way of a buffer or a divider from a third clock pulse, a fourth clock pulse is generated by way of a buffer or a divider from a fifth clock pulse, and the third clock pulse is supplied to the first latch group by way of a buffer and the fifth clock pulse is supplied to the second latch group by way of a buffer.
摘要翻译： 在包含宏的半导体集成电路装置中，在提供给该母电路中的锁存器的时钟脉冲与提供给该宏中的锁存器的时钟脉冲之间发生偏斜。 这些时钟偏差阻碍了半导体集成电路器件时钟频率的高频率操作，使得半导体集成电路器件不能以高速运行。 在具有第一时钟处理器装置的半导体集成电路装置中，产生第三时钟脉冲，使得以相同相位和相同频率输入第一时钟脉冲和第二时钟脉冲，第二时钟处理器装置产生第五个时钟脉冲， 以相同相位和相同频率输入第三和第四时钟脉冲，以及由多个锁存器组成的第一锁存器组和第二锁存器组，并且在该半导体集成电路器件中，第二时钟脉冲以方式产生 的第三时钟脉冲的缓冲器或分频器，通过来自第五时钟脉冲的缓冲器或分频器产生第四时钟脉冲，并且第三时钟脉冲通过缓冲器提供给第一锁存器组，并且 第五时钟脉冲通过缓冲器提供给第二锁存器组。
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公开(公告)号：US06679286B2
公开(公告)日：2004-01-20
申请号：US10201274
申请日：2002-07-24
申请人： Nobuhide Kato , Hiroyuki Mizuno
发明人： Nobuhide Kato , Hiroyuki Mizuno
IPC分类号： F16K3120
CPC分类号： F16K33/00 , F16K21/185 , F16K31/24 , G01F23/74 , Y10T137/7423 , Y10T137/7439 , Y10T137/7465 , Y10T137/8342
摘要： A compact ball tap with 1 a water level switch which comprises a guide standpipe 5 vertically arranged in a tank T, a float 6 slidably installed on the guide standpipe 5, a valve 3, a lever 4 controlling an open-close action of the valve 3 connected with the float 6, and a water level switch 29 transmitting predetermined control signals when the float 6 shifts to a predetermined water level, wherein one float 6 is shared by the ball tap 1 and the water level switch 29.
摘要翻译： 具有1个水位开关的紧凑型球形水龙头，其包括垂直布置在罐T中的导向立管5，可滑动地安装在导向立管5上的浮子6，阀3，控制阀的开闭动作的杆4 3与水平开关29连接，水位开关29在浮子6转移到预定的水位时发送预定的控制信号，其中一个浮子6由球阀1和水位开关29共用。
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公开(公告)号：US06630857B2
公开(公告)日：2003-10-07
申请号：US10024039
申请日：2001-12-21
IPC分类号： H03K301
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit apparatus includes a first controlled circuit having at least one MOS transistor and a substrate bias control unit for generating a substrate bias voltage of the MOS transistor, wherein when the substrate bias control unit is set in a first mode, a comparatively large current is allowed to flow between the source and drain of the MOS transistor, while when the substrate bias control unit is set in a second mode, the comparatively large current allowed to flow between the source and drain of the MOS transistor is controlled to a current of smaller value. The value of the substrate bias applied to the first controlled circuit is larger in the second mode than in the first mode for the substrate bias of the PMOS transistor, and smaller in the second mode than in the first mode for the substrate bias of the NMOS transistor. The power supply voltage applied to the first controlled circuit is controlled to a smaller value in the second mode than in the first mode.
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公开(公告)号：US06597220B2
公开(公告)日：2003-07-22
申请号：US10241505
申请日：2002-09-12
IPC分类号： H03L706
CPC分类号： H03K19/018585 , H03K19/00384
摘要： A semiconductor integrated circuit includes a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit corresponds to the frequency of the reference clock signal.
摘要翻译： 半导体集成电路包括由p沟道MIS晶体管和n沟道MIS晶体管形成的逻辑电路，由p沟道MIS晶体管和n沟道MIS晶体管形成的可变振荡频率的第一振荡电路，控制 产生用于控制p沟道和n沟道MIS晶体管的阈值电压的控制信号的电路，以及根据操作模式产生不同频率的多个参考时钟信号的第二振荡电路。 控制电路接收参考时钟信号并利用控制信号控制第一振荡电路，使得第一振荡电路的振荡频率对应于参考时钟信号的频率。
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公开(公告)号：US06593026B1
公开(公告)日：2003-07-15
申请号：US09695278
申请日：2000-10-25
IPC分类号： H01M236
CPC分类号： H01M10/34 , H01M2/36 , H01M10/4285
摘要： The present invention provides a sealed battery, in which leakage can be detected in reliable manner, a method for manufacturing the sealed battery, and a method for detecting leakage of the sealed battery. The invention provides a sealed battery containing helium, a method for manufacturing the sealed battery, and a method for detecting leakage. From inside a battery case sealed except an electrolyte inlet, the air is withdrawn, and pressure is applied by a gas containing helium under pressure higher than the atmospheric pressure through the electrolyte inlet. The electrolyte is injected, and after the electrolyte and the gas containing helium have been injected, the electrolyte inlet is sealed.
摘要翻译： 本发明提供一种可靠地检测泄漏的密封电池，密封电池的制造方法以及密封电池的泄漏检测方法。 本发明提供一种含有氦的密封电池，密封电池的制造方法以及泄漏检测方法。 从除了电解质入口之外密封的电池壳体内部，空气被抽出，并且在压力高于大气压力的压力下通过含有氦气的气体通过电解质入口施加压力。 电解液被注入，在注入电解质和含氦气体之后，密封电解液入口。
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公开(公告)号：US06505599B1
公开(公告)日：2003-01-14
申请号：US09656159
申请日：2000-09-06
申请人： Zenichiro Mashiki , Jun Maemura , Rihito Kaneko , Masahide Nagano , Senji Kato , Hiroyuki Mizuno
发明人： Zenichiro Mashiki , Jun Maemura , Rihito Kaneko , Masahide Nagano , Senji Kato , Hiroyuki Mizuno
IPC分类号： F02D4102
CPC分类号： F02D41/3076 , F02B2075/125 , F02D41/0032 , F02D41/3029 , F02M25/08 , Y02T10/128
摘要： A fuel vapor treating mechanism includes a canister for adsorbing fuel vapor produced in a fuel feed system. The treating mechanism purges the fuel vapor adsorbed by the canister, along with air, to an intake system of the engine. An ECU computes a value representing the flow rate of the purged gas as a value that represents the capability of the treating apparatus. The ECU sets a decision value in accordance with the amount of the fuel vapor produced in the fuel feed system. The decision value represents a required capability of the treating mechanism. When the value representing the capability is less than the decision value, the ECU prohibits stratified charge combustion and causes the engine to perform homogeneous charge combustion. Therefore, as many opportunities as possible are provided to perform stratified charge combustion, which improves fuel efficiency.
摘要翻译： 燃料蒸汽处理机构包括用于吸附在燃料供给系统中产生的燃料蒸气的罐。 处理机构将由罐吸附的燃料蒸气与空气一起清洗到发动机的进气系统。 ECU计算表示净化气体的流量的值作为表示处理装置的能力的值。 ECU根据在燃料供给系统中产生的燃料蒸汽的量来设定决定值。 决策值代表治疗机制所需的能力。 当表示能力的值小于决定值时，ECU禁止分层充气燃烧，并使发动机进行均匀的充气燃烧。 因此，提供尽可能多的机会来执行分层充气燃烧，这提高燃料效率。
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90.发明授权公开(公告)号：US06504400B2
公开(公告)日：2003-01-07
申请号：US10122178
申请日：2002-04-16
申请人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
发明人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
IPC分类号： H03K190175
CPC分类号： H03K3/356113 , H01L2924/0002 , H03K3/356104 , H01L2924/00
摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
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