公开(公告)号：US08962420B2

公开(公告)日：2015-02-24

申请号：US12553475

申请日：2009-09-03

申请人： Andreas Kurz ,  Roman Boschke ,  James Buller ,  Andy Wei

发明人： Andreas Kurz ,  Roman Boschke ,  James Buller ,  Andy Wei

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L27/06 ,  H01L21/84 ,  H01L27/12 ,  H01L49/02

CPC分类号： H01L27/0629 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/20

摘要： An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance.

摘要翻译： 嵌入或埋入的电阻结构可以通过半导体材料的非晶化并随后在多晶态中重新结晶而形成，从而提供与诸如多晶硅电阻器的常规多晶电阻器的高度兼容性，同时避免专用 多晶材料。 因此，多晶电阻器可以有利地与基于非硅栅电极材料的复杂晶体管架构组合，同时还提供相对于寄生电容的电阻器的高性能。

公开(公告)号：US08664103B2

公开(公告)日：2014-03-04

申请号：US13154578

申请日：2011-06-07

申请人： Klaus Hempel ,  Andy Wei ,  Robert Binder ,  Joachim Metzger

发明人： Klaus Hempel ,  Andy Wei ,  Robert Binder ,  Joachim Metzger

IPC分类号： H01L21/3205

CPC分类号： H01L29/66545 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a reduced threshold voltage (Vt) may be achieved in HK/MG transistor elements that are manufactured based on replacement gate electrode integrations. One illustrative method disclosed herein includes forming a first metal gate electrode material layer above a gate dielectric material layer having a dielectric constant of approximately 10 or greater. The method further includes exposing the first metal gate electrode material layer to an oxygen diffusion process, forming a second metal gate electrode material layer above the first metal gate electrode material layer, and adjusting an oxygen concentration gradient and a nitrogen concentration gradient in at least the first metal gate electrode material layer and the gate dielectric material layer.

摘要翻译： 通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中可以在基于替换栅极集成制造的HK / MG晶体管元件中实现降低的阈值电压（Vt）。 本文公开的一种说明性方法包括在介电常数约为10或更大的栅介质材料层上形成第一金属栅电极材料层。 该方法还包括将第一金属栅电极材料层暴露于氧扩散过程，在第一金属栅电极材料层上形成第二金属栅电极材料层，并且至少在第一金属栅电极材料层上调整氧浓度梯度和氮浓度梯度 第一金属栅电极材料层和栅介质材料层。

公开(公告)号：US08652889B2

公开(公告)日：2014-02-18

申请号：US13372837

申请日：2012-02-14

申请人： Andy Wei ,  Peter Baars ,  Richard Carter ,  Frank Ludwig

发明人： Andy Wei ,  Peter Baars ,  Richard Carter ,  Frank Ludwig

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.

摘要翻译： 当形成复杂的半导体器件时，与平面晶体管组合的三维晶体管可以通过在早期制造阶段中形成半导体翅片（即，在形成浅沟槽隔离时）基于替代栅极接近和自对准接触元件而形成 其中半导体翅片的最终电有效高度可以在提供自对准接触元件之后和在更换栅极接近期间被调整。

公开(公告)号：US20130137257A1

公开(公告)日：2013-05-30

申请号：US13305131

申请日：2011-11-28

申请人： Andy Wei ,  Peter Baars ,  Erik Geiss

发明人： Andy Wei ,  Peter Baars ,  Erik Geiss

IPC分类号： H01L21/28

CPC分类号： H01L21/28079 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.

摘要翻译： 本文公开了使用牺牲栅电极和牺牲自对准触点形成半导体器件的各种方法。 在一个示例中，该方法包括形成由第一材料构成的两个间隔开的牺牲栅电极，形成包括第二材料的牺牲接触结构，其中第二材料相对于所述第一材料可选择性地蚀刻，并且执行蚀刻 在两个间隔开的牺牲栅电极和牺牲接触结构之间进行选择性地相对于牺牲接触结构选择性地去除两个间隔开的牺牲栅极电极结构。

公开(公告)号：US08334569B2

公开(公告)日：2012-12-18

申请号：US13454177

申请日：2012-04-24

申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

IPC分类号： H01L29/66

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/78

摘要： In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

摘要翻译： 在复杂的半导体器件中，应变诱导半导体合金可以通过基于湿化学蚀刻工艺形成空腔来定位，靠近沟道区域，其可以相对于不同的晶体取向具有各向异性蚀刻行为。 在一个实施方案中，可以使用TMAH，除了各向异性蚀刻行为之外，还显示出相对于二氧化硅的高蚀刻选择性，从而使极细的蚀刻停止层可以进一步减少与沟道区的偏移 同时不会对整体过程变化造成过分的不利影响。

公开(公告)号：US20120223309A1

公开(公告)日：2012-09-06

申请号：US13474934

申请日：2012-05-18

申请人： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

发明人： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC分类号： H01L23/58

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US08183100B2

公开(公告)日：2012-05-22

申请号：US12562437

申请日：2009-09-18

申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Casey Scott

IPC分类号： H01L21/84

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/78

摘要： In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

摘要翻译： 在复杂的半导体器件中，应变诱导半导体合金可以通过基于湿化学蚀刻工艺形成空腔来定位，靠近沟道区域，其可以相对于不同的晶体取向具有各向异性蚀刻行为。 在一个实施方案中，可以使用TMAH，除了各向异性蚀刻行为之外，还显示出相对于二氧化硅的高蚀刻选择性，从而使极细的蚀刻停止层可以进一步减少与沟道区的偏移 同时不会对整体过程变化造成过分的不利影响。

公开(公告)号：US20110294269A1

公开(公告)日：2011-12-01

申请号：US13113698

申请日：2011-05-23

申请人： Frank Wirbeleit ,  Andy Wei

发明人： Frank Wirbeleit ,  Andy Wei

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.

摘要翻译： 当在半导体器件的有源区域中形成空腔以引入应变引起的半导体材料时，可以通过使用注入工艺来实现优异的均匀性，以便选择性地改变有源区域的暴露部分的蚀刻行为。 以这种方式，可以以高度的灵活性来调节空腔的基本构造，同时可以降低对图案加载效果的依赖性。 因此，可以实现晶体管特性的显着降低的变化。

公开(公告)号：US08053273B2

公开(公告)日：2011-11-08

申请号：US12504758

申请日：2009-07-17

申请人： Thorsten Kammler ,  Andy Wei ,  Ina Ostermay

发明人： Thorsten Kammler ,  Andy Wei ,  Ina Ostermay

IPC分类号： H01L21/00

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.

摘要翻译： 可以在漏极和源极区域中形成硅/碳合金，其中另一部分可以作为相对于栅电极材料的偏移减小的原位掺杂材料提供。 为此，在一个说明性实施例中，可以在超高真空环境中的低温下使用包括多个生长/蚀刻循环的循环外延生长工艺，从而获得基本上从底部到顶部的填充行为。

公开(公告)号：US08039878B2

公开(公告)日：2011-10-18

申请号：US12821308

申请日：2010-06-23

申请人： Igor Peidous ,  Thorsten Kammler ,  Andy Wei

发明人： Igor Peidous ,  Thorsten Kammler ,  Andy Wei

IPC分类号： H01L21/76

CPC分类号： H01L29/7843 ,  H01L21/26506 ,  H01L29/51 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.

摘要翻译： 通过相对于硅层的结晶特性适当地定向沟道长度方向，与常规技术相比，应变硅/碳材料的应力诱导效应可以显着提高。 在一个说明性实施例中，通道可以沿着（100）表面取向沿着<100>方向取向，从而提供大约四分之一的电子迁移率增加。