公开(公告)号：US10985048B2

公开(公告)日：2021-04-20

申请号：US16732367

申请日：2020-01-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US10347526B1

公开(公告)日：2019-07-09

申请号：US15951683

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a gate structure, and a conductive element. The gate structure is on the substrate. The gate structure includes a gate electrode and a cap layer on the gate electrode. The conductive element is adjoined with an outer surface of the gate structure. The conductive element includes a lower conductive portion and an upper conductive portion electrically connected on the lower conductive portion and adjoined with the cap layer. The lower conductive portion and the upper conductive portion have an interface therebetween. The interface is below an upper surface of the cap layer.

公开(公告)号：US20190172752A1

公开(公告)日：2019-06-06

申请号：US15830008

申请日：2017-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823475 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.

公开(公告)号：US09870951B2

公开(公告)日：2018-01-16

申请号：US15599430

申请日：2017-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L23/535 ,  H01L27/088 ,  H01L23/485

CPC classification number: H01L21/823475 ,  H01L21/0206 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/0226 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7856

Abstract: A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess.

公开(公告)号：US09847398B1

公开(公告)日：2017-12-19

申请号：US15208616

申请日：2016-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/423 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; a spacer around the gate structure; a contact etch stop layer (CESL) on the spacer; an interlayer dielectric (ILD) layer adjacent to one side of the gate structure and contacting the CESL; and a contact plug adjacent to another side of the gate structure and contacting the CESL.

公开(公告)号：US09793380B2

公开(公告)日：2017-10-17

申请号：US14794821

申请日：2015-07-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.

公开(公告)号：US20170294508A1

公开(公告)日：2017-10-12

申请号：US15144842

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq ,  Tsung-Mu Yang

IPC: H01L29/06 ,  H01L21/768 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.

公开(公告)号：US09786510B2

公开(公告)日：2017-10-10

申请号：US14512475

申请日：2014-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

IPC: H01L21/308 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/308 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66818

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

公开(公告)号：US09780169B2

公开(公告)日：2017-10-03

申请号：US14876844

申请日：2015-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Yu-Cheng Tung ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first conductivity region and a second conductivity region defined thereon, a plurality of first fin structures and at least one first gate structure disposed on the substrate and within the first conductivity region, a plurality of second fin structures and at least one second gate structure disposed on the substrate and within the second conductivity region, at least two first crown epitaxial layers disposed within the first conductivity region, a plurality of second epitaxial layers disposed within the second conductivity region, where the shape of the first crown epitaxial layer is different from that of the second epitaxial layer.

公开(公告)号：US09685385B1

公开(公告)日：2017-06-20

申请号：US15226929

申请日：2016-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L21/823821 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/66795

Abstract: The present invention provides a method for forming a semiconductor device, including the following steps: first, a substrate is provided, at least one gate is formed on the substrate, a contact etching stop layer (CESL) and a first dielectric layer are formed on the substrate in sequence, afterwards, a first etching process is performed to remove the first dielectric layer, and to expose a top surface and at least one sidewall of the etching stop layer, next, a second etching process is performed to partially remove the contact etching stop layer, and to form at least one epitaxial recess in the substrate. Afterwards, an epitaxial process is performed, to form an epitaxial layer in the epitaxial recess, and a contact structure is then formed on the epitaxial layer.