公开(公告)号：US20180331044A1

公开(公告)日：2018-11-15

申请号：US15624498

申请日：2017-06-15

Applicant: United Microelectronics Corp.

Inventor： Yi-Yu Wu ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Bin-Siang Tsai

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53257 ,  H01L21/02068 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/53295

Abstract: A semiconductor device including a tungsten contact structure formed in a first dielectric layer on a substrate is provided. The tungsten contact structure contains a seam structure. A tungsten oxide layer is formed at least on a sidewall of the seam structure.

公开(公告)号：US09917007B2

公开(公告)日：2018-03-13

申请号：US15188621

申请日：2016-06-21

Applicant: United Microelectronics Corp.

Inventor： Yi-Yu Wu ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144

Abstract: A method of forming an opening pattern including the following steps is provided. An ultra low dielectric constant layer, a dielectric hard mask layer and a patterned metal hard mask layer are sequentially formed on a substrate. A portion of the dielectric hard mask layer is removed to form a patterned dielectric hard mask layer by using the patterned metal hard mask layer as a mask. The patterned metal hard mask layer is removed after forming the patterned dielectric hard mask layer. A portion of the ultra low dielectric constant layer is removed to form a first opening by using the patterned dielectric hard mask layer as a mask.

公开(公告)号：US12205909B2

公开(公告)日：2025-01-21

申请号：US18138752

申请日：2023-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

公开(公告)号：US20250008743A1

公开(公告)日：2025-01-02

申请号：US18885727

申请日：2024-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the first thickness is greater than the second thickness

公开(公告)号：US12108691B2

公开(公告)日：2024-10-01

申请号：US18324173

申请日：2023-05-26

Applicant: United Microelectronics Corp.

Inventor： Chich-Neng Chang ,  Da-Jun Lin ,  Shih-Wei Su ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/24 ,  H10B63/30 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

公开(公告)号：US12016250B2

公开(公告)日：2024-06-18

申请号：US17725511

申请日：2022-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

公开(公告)号：US20240162208A1

公开(公告)日：2024-05-16

申请号：US18077192

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chih-Wei Chang ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L25/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778 ,  H01L31/0224 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/18 ,  H03H3/08 ,  H03H9/02

CPC classification number: H01L25/167 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/454 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786 ,  H01L31/022408 ,  H01L31/03044 ,  H01L31/035236 ,  H01L31/1856 ,  H03H3/08 ,  H03H9/02976

Abstract: A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.

公开(公告)号：US11849649B2

公开(公告)日：2023-12-19

申请号：US17573641

申请日：2022-01-12

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H10N50/80 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10N50/01 ,  H10N50/85

Abstract: A method for fabricating memory cell of magnetoresistive RAM includes forming a memory stack structure on a first electrode layer. The memory stack structure includes a SAF layer to serve as a pinned layer; a magnetic free layer and a barrier layer sandwiched between the SAF layer and the magnetic free layer. A second electrode layer is then formed on the memory stack structure. The SAF layer includes a first magnetic layer, a second magnetic layer, and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first and second magnetic layers, and the second metal element of the first magnetic layer and the second magnetic layer interfaces with the spacer layer.

公开(公告)号：US20230378275A1

公开(公告)日：2023-11-23

申请号：US17844746

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/205 ,  H01L29/7786

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A silicon-rich tensile stress layer is formed on the III-V compound barrier layer. An annealing process is performed after the silicon-rich tensile stress layer is formed. A part of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer for forming a silicon-doped III-V compound barrier layer by the annealing process.

公开(公告)号：US20230352557A1

公开(公告)日：2023-11-02

申请号：US17833885

申请日：2022-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chih-Wei Chang ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L29/66 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/45 ,  H01L29/423 ,  H01L29/778 ,  H01L21/265 ,  H01L29/40

CPC classification number: H01L29/66462 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/452 ,  H01L29/42316 ,  H01L29/7786 ,  H01L21/26546 ,  H01L29/401

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A passivation layer is formed on the III-V compound barrier layer. A silicon layer is formed on the passivation layer, the III-V compound barrier layer, and the III-V compound semiconductor layer. A silicon implantation process is performed to the III-V compound semiconductor layer for forming a source doped region and a drain doped region in the III-V compound semiconductor layer under the silicon layer. A source electrode and a drain electrode are formed on the silicon layer. A source silicide layer is formed between the source electrode and the source doped region, and a drain silicide layer is formed between the drain electrode and the drain doped region. The source silicide layer and the drain silicide layer are partly formed on the passivation layer.