公开(公告)号：US07193267B2

公开(公告)日：2007-03-20

申请号：US10971204

申请日：2004-10-21

申请人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： H01L29/76

CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  H01L27/24

摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

摘要翻译： 提供了电阻式交叉点存储器件，以及制造和使用方法。 存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。 在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 在电阻性存储器材料和下电极之间的界面处形成二极管，其可以形成为掺杂区域。 电阻性交叉点存储器件通过在衬底内掺杂一个极性而形成，然后将相反极性的线的掺杂区域形成二极管。 然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。 然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

公开(公告)号：US06849564B2

公开(公告)日：2005-02-01

申请号：US10376796

申请日：2003-02-27

申请人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang ,  Fengyan Zhang

IPC分类号： G11C13/00 ,  H01L27/10 ,  H01L27/24 ,  H01L21/00

CPC分类号： H01L27/24 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  H01L27/10

摘要： A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate; forming an n-doped buried layer (buried n layer) of silicon overlying the substrate; forming n-doped silicon sidewalls overlying the buried n layer; forming a p-doped well of silicon (p-well) overlying the buried n layer; and, forming a 1R1D R-RAM array overlying the p-well. Typically, the combination of the buried n layer and the n-doped sidewalls form an n-doped well (n-well) of silicon. Then, the p-well is formed inside the n-well. In other aspects, the p-well has sidewalls, and the method further comprises: forming an oxide insulator overlying the p-well sidewalls, between the n-well and the R-RAM array.

摘要翻译： 提供具有浮动p-well的低电容单电阻/单二极管（1R1D）R-RAM阵列。 该制造方法包括：形成集成电路（IC）衬底; 形成覆盖在衬底上的硅的n掺杂掩埋层（n层）; 形成覆盖掩埋n层的n掺杂硅侧壁; 形成覆盖在掩埋n层上的硅（p阱）的p掺杂阱; 并且形成覆盖p阱的1R1D R-RAM阵列。 通常，掩埋n层和n掺杂侧壁的组合形成硅的n掺杂阱（n阱）。 然后，p阱形成在n阱内。 在其他方面，p阱具有侧壁，并且该方法还包括：在n阱和R-RAM阵列之间形成覆盖p阱侧壁的氧化物绝缘体。

公开(公告)号：US06709942B2

公开(公告)日：2004-03-23

申请号：US10385390

申请日：2003-03-10

申请人： Wei Pan ,  Sheng Teng Hsu

发明人： Wei Pan ,  Sheng Teng Hsu

IPC分类号： H01L2120

CPC分类号： H01L27/222 ,  B82Y10/00 ,  G11C11/15

摘要： An MRAM device includes a substrate; plural conductive lines, including a bit line and a word line; and a MTJ stack including a pair of magnetic yoke structures, wherein each of said yoke structures surrounds a conductive line. A method of fabricating a magnetic yoke in an MRAM structure includes preparing a substrate; forming a first conductive line on the substrate; fabricating a MTJ stack, including fabricating a first magnetic yoke structure about the first conductive line; forming a second conductive line on the MTJ stack; fabricating a second magnetic yoke about the second conductive line; depositing a layer of oxide on the structure; and metallizing the structure.

摘要翻译： MRAM器件包括衬底; 多个导线，包括位线和字线; 以及包括一对磁轭结构的MTJ堆叠，其中每个所述轭结构围绕导电线。 一种在MRAM结构中制造磁轭的方法包括：制备衬底; 在所述基板上形成第一导电线; 制造MTJ堆叠，包括围绕第一导电线制造第一磁轭结构; 在MTJ堆叠上形成第二导线; 围绕第二导线制造第二磁轭; 在结构上沉积一层氧化物; 并且对结构进行金属化。

公开(公告)号：US06555467B2

公开(公告)日：2003-04-29

申请号：US09967594

申请日：2001-09-28

申请人： Sheng Teng Hsu ,  Wei Pan

发明人： Sheng Teng Hsu ,  Wei Pan

IPC分类号： H01L2951

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inter-level insulator structure is provided having an effective insulator dielectric constant approaching 1. An embodiment of the inter-level insulator comprises a first metal layer comprising a first plurality of metal lines; a second metal layer comprising a second plurality of metal lines, and at least one via connected to the first metal layer; and an air gap interposed between the first metal layer and the second metal layer. In one embodiment, the air gap is also present between metal lines on either metal layer, such that air gaps act as intra-level as well as inter-level insulators. A method is also provided to deposit and pattern a sacrificial polymer, and form metal layers. The sacrificial polymer is capable of being decomposed to become air gaps during annealing.

摘要翻译： 提供具有接近1的有效绝缘体介电常数的级间绝缘体结构。层间绝缘体的实施例包括包含第一多个金属线的第一金属层; 包括第二多个金属线的第二金属层和连接到第一金属层的至少一个通孔; 以及插入在第一金属层和第二金属层之间的气隙。 在一个实施例中，空气间隙也存在于金属层上的金属线之间，使得气隙作为内部级别以及级间绝缘体。 还提供了沉积和图案化牺牲聚合物并形成金属层的方法。 牺牲聚合物能够在退火过程中分解成气隙。

公开(公告)号：US06548849B1

公开(公告)日：2003-04-15

申请号：US10061974

申请日：2002-01-31

申请人： Wei Pan ,  Sheng Teng Hsu

发明人： Wei Pan ,  Sheng Teng Hsu

IPC分类号： H01L27108

CPC分类号： H01L27/222 ,  B82Y10/00 ,  G11C11/15

摘要： An MRAM device includes a substrate; plural conductive lines, including a bit line and a word line; and a MTJ stack including a pair of magnetic yoke structures, wherein each of said yoke structures surrounds a conductive line. A method of fabricating a magnetic yoke in an MRAM structure includes preparing a substrate; forming a first conductive line on the substrate; fabricating a MTJ stack, including fabricating a first magnetic yoke structure about the first conductive line; forming a second conductive line on the MTJ stack; fabricating a second magnetic yoke about the second conductive line; depositing a layer of oxide on the structure; and metallizing the structure.

摘要翻译： MRAM器件包括衬底; 多个导线，包括位线和字线; 以及包括一对磁轭结构的MTJ堆叠，其中每个所述轭结构围绕导电线。 一种在MRAM结构中制造磁轭的方法包括：制备衬底; 在所述基板上形成第一导电线; 制造MTJ堆叠，包括围绕第一导电线制造第一磁轭结构; 在MTJ堆叠上形成第二导线; 围绕第二导线制造第二磁轭; 在结构上沉积一层氧化物; 并且对结构进行金属化。

公开(公告)号：US06194310B1

公开(公告)日：2001-02-27

申请号：US09585680

申请日：2000-06-01

申请人： Sheng Teng Hsu ,  Douglas James Tweet ,  Wei Pan ,  David Russell Evans

发明人： Sheng Teng Hsu ,  Douglas James Tweet ,  Wei Pan ,  David Russell Evans

IPC分类号： H01L214763

CPC分类号： H01L21/76864 ,  H01L21/28556 ,  H01L2221/1078

摘要： A method of forming conducting diffusion barriers is provided. The method produces substantially amorphous conducting diffusion barriers by depositing materials with varying ratios of elements throughout the diffusion barrier. Diffusion barriers of metal nitride, metal silicon nitride, are deposited using CVD, PECVD, or ALCVD, by depositing material with a first ratio of elements and then depositing substantially identical material with a different ratio of elements. The actual elements used are the same, but the ratio is changed. By changing the ratio of the elements within the same diffusion barrier, density variations are produced, and the material is not able to form undesirable polycrystalline structures.

摘要翻译： 提供形成导电扩散阻挡层的方法。 该方法通过在整个扩散阻挡层中沉积具有不同比例的元素的材料来产生基本上非晶的导电扩散阻挡层。 使用CVD，PECVD或ALCVD沉积金属氮化物，金属氮化硅的扩散屏障，通过以第一比例的元素沉积材料，然后沉积具有不同比例元素的基本相同的材料。 使用的实际元素是相同的，但是比例是改变的。 通过改变相同扩散阻挡层内的元素的比例，产生密度变化，并且材料不能形成不期望的多晶结构。

公开(公告)号：US07905013B2

公开(公告)日：2011-03-15

申请号：US11809959

申请日：2007-06-04

申请人： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

IPC分类号： H01K3/10

CPC分类号： A61N1/0543 ,  B82Y15/00 ,  B82Y30/00 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T428/24998

摘要： An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

摘要翻译： 提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。 该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。 基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。 电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

公开(公告)号：US07811913B2

公开(公告)日：2010-10-12

申请号：US11312967

申请日：2005-12-19

申请人： Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/265

CPC分类号： H01L31/105 ,  H01L31/1808 ,  H01L31/1864 ,  Y02E10/50 ,  Y02P70/521 ,  Y10S438/933

摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.

摘要翻译： 制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在硼掺杂的锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火来活化N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

公开(公告)号：US07759756B2

公开(公告)日：2010-07-20

申请号：US12025618

申请日：2008-02-04

申请人： Jong-Jan Lee ,  Sakae Wada ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Sakae Wada ,  Sheng Teng Hsu

IPC分类号： H01L31/00 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14647 ,  H01L27/14689

摘要： A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The single photodiode includes the n doped substrate, a p doped layer overlying the substrate, and an n doped layer cathode overlying the p doped layer.

摘要翻译： 提供了双像素全色互补金属氧化物半导体（CMOS）成像器，以及相关的制造工艺。 两个独立像素用于三色检测。 第一像素是单个光电二极管，第二像素具有以堆叠结构内置的两个光电二极管。 两个光电二极管堆叠包括n掺杂衬底，底部光电二极管和顶部光电二极管。 底部光电二极管具有覆盖衬底的底部p掺杂层和覆盖底部p掺杂层的底部n掺杂层阴极。 顶部光电二极管具有覆盖底部n掺杂层的顶部p掺杂层和覆盖顶部p掺杂层的顶部n掺杂层阴极。 单个光电二极管包括n掺杂衬底，覆盖衬底的p掺杂层和覆盖p掺杂层的n掺杂层阴极。

公开(公告)号：US07723729B2

公开(公告)日：2010-05-25

申请号：US12036396

申请日：2008-02-25

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L31/0312 ,  H01L29/20 ,  H01L29/06

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/045 ,  H01L29/0673

摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where x≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.

摘要翻译： 提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。 该方法形成Si衬底。 在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。 化合物半导体选择性沉积在Si纳米线尖端上。 横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。 通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或SiXNY，其中x和nlE; 3和Y和nlE; 4。 化合物半导体可以是GaN，GaAs，GaAlN或SiC。 在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。