公开(公告)号：US20070061653A1

公开(公告)日：2007-03-15

申请号：US11474121

申请日：2006-06-23

Applicant: Prashant Dubey ,  Amit Kashyap

Inventor： Prashant Dubey ,  Amit Kashyap

IPC: G01R31/28

CPC classification number: G11C29/802 ,  G11C29/4401 ,  G11C29/812

Abstract: The present invention provides a built-in self-repairable memory. The invention repairs a faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses a lesser number of fuses to actually make a repair and thus results in a yield enhancement. The fuse data is stored in a compressed form and then decompressed as a restore happens at the power on. The fuse data interface with the memory to be repaired is serial. The serial links decreases the routing congestion and hence gain in area as well as gain in yield (due to lesser defects and reduced area)

Abstract translation: 本发明提供了一种内置的可自我修复的存储器。 本发明通过硬保险丝以及片上存储器中的可用冗余来修复故障IC。 由于故障不存在于所有存储器中，本发明使用较少数量的保险丝来实际进行修理，从而导致产量提高。 熔丝数据以压缩形式存储，然后在上电时恢复发生解压缩。 与要修复的存储器的保险丝数据接口是串行的。 串行链路减少路由拥塞，从而减少区域内的增益以及产量增益（由于较小的缺陷和减少的区域）

公开(公告)号：US07183813B2

公开(公告)日：2007-02-27

申请号：US10985661

申请日：2004-11-10

Applicant: Sunil Chandra Kasanyal ,  Hari Bilash Dubey

Inventor： Sunil Chandra Kasanyal ,  Hari Bilash Dubey

IPC: H03K5/22

CPC classification number: H04L25/0286 ,  H03K5/133 ,  H04L25/0272

Abstract: The present invention provides a Differential Signaling line driver including a pre-emphasis circuit, which boosts the output drive current without any delay whenever there is a transition in the input signal to the driver, using the input signal itself to provide the pre-emphasis through a current steering circuit that switches the direction of drive currents to provide a differential output signal. A delayed signal is then used to disable the pre-emphasis after a short period.

Abstract translation: 本发明提供了一种差分信号线路驱动器，其包括预加重电路，每当输入信号转换到驱动器时​​，无需任何延迟即可提升输出驱动电流，使用输入信号本身提供预加重 电流转向电路，其切换驱动电流的方向以提供差分输出信号。 然后使用延迟信号在短时间之后禁用预加重。

公开(公告)号：US20070016826A1

公开(公告)日：2007-01-18

申请号：US11441815

申请日：2006-05-26

Applicant: Prashant Dubey

Inventor： Prashant Dubey

IPC: G06F11/00 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/12015 ,  G11C29/003 ,  G11C29/1201 ,  G11C29/20 ,  G11C29/40 ,  G11C2029/0405 ,  G11C2029/3602

Abstract: A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. Memories can fail at high speed due to glitches (unwanted pulses which can at times behave as invalid clocks and destroy the functionality of synchronous systems) produced in decoding, the slow precharge of bitlines or the slow sensing of the sense amplifiers. The memory architecture incorporates structured DFT techniques to separately detect these failures.

Abstract translation: 可配置的存储器架构包括集成在所述存储器中的内置测试机制，以在随机存取存储器（RAM）中支持非常有效的内置自检，在面积和速度方面大大减少了开销。 存储器由于在解码中产生的毛刺（有时表现为无效时钟，破坏同步系统的功能的有害脉冲），位线的慢预充电或读出放大器的慢感测，可能会高速故障。 内存架构包含结构化DFT技术，以分别检测这些故障。

公开(公告)号：US20070011539A1

公开(公告)日：2007-01-11

申请号：US11318347

申请日：2005-12-23

Applicant: Danish Syed ,  Vishal Srivastava

Inventor： Danish Syed ,  Vishal Srivastava

IPC: G01R31/28

CPC classification number: G01R31/31855 ,  G01R31/318519 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17764 ,  H03K19/17772

Abstract: A self test structure for interconnect and logic element testing in programmable devices including a plurality of logic elements; an interconnect structure for connecting the logic elements; SRAM based configuration latches for configuring the interconnect structure; test configuration circuitry for configuring any desired set of logic elements, interconnect structure and configuration latches during reset state that links the logic elements and interconnect structure to form a complete path between the interface points of the programmable logic device to enable testing of the desired elements in the complete path.

Abstract translation: 一种用于在包括多个逻辑元件的可编程设备中进行互连和逻辑元件测试的自检结构; 用于连接逻辑元件的互连结构; 用于配置互连结构的基于SRAM的配置锁存器; 测试配置电路，用于在复位状态期间配置任何期望的逻辑元件集，互连结构和配置锁存器，所述复位状态链接逻辑元件和互连结构，以在可编程逻辑器件的接口点之间形成完整的路径，以使得能够测试所需的元件 完整的路径。

公开(公告)号：US07109749B2

公开(公告)日：2006-09-19

申请号：US10449750

申请日：2003-05-29

Applicant: Namerita Khanna ,  Parvesh Swami ,  Deepak Agarwal

Inventor： Namerita Khanna ,  Parvesh Swami ,  Deepak Agarwal

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K3/012 ,  H03K3/037 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17784

Abstract: A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.

Abstract translation: 一种可编程逻辑器件，用于为顺序逻辑和数据存储功能提供功率消耗降低，包括至少一个电路装置，其可配置为在电路时钟选定的一个或两个边缘上工作的双边沿触发触发器。

公开(公告)号：US20060123292A1

公开(公告)日：2006-06-08

申请号：US11190492

申请日：2005-07-26

Applicant: Vishal Bansal ,  Deepak Baranwal

Inventor： Vishal Bansal ,  Deepak Baranwal

IPC: G01R31/28

CPC classification number: H04J3/047 ,  G01R31/31723 ,  H03K19/1732

Abstract: A system and method for multiplexing an integrated circuit pin include a plurality of registers for storing bit values; a plurality of functions to be multiplexed on receiving the bit values; a decoding logic for decoding the bit values for selecting at least one of the functions; a plurality of pads connected to the plurality of functions and the decoding logic; and external pin/pins acting as inputs/outputs for the selected functionality depending upon the bit values.

Abstract translation: 用于复用集成电路引脚的系统和方法包括用于存储位值的多个寄存器; 多个功能，在接收到比特值时进行多路复用; 解码逻辑，用于对所述位值进行解码以选择所述功能中的至少一个; 连接到所述多个功能的多个焊盘和所述解码逻辑; 并且根据位值，外部引脚/引脚作为所选功能的输入/输出。

公开(公告)号：US07058911B2

公开(公告)日：2006-06-06

申请号：US10321297

申请日：2002-12-17

Applicant: Balwant Singh

Inventor： Balwant Singh

IPC: G06F17/50

CPC classification number: G11C29/50012 ,  G11C29/50

Abstract: A system for measuring a timing skew between two digital signals may include a clock generator for generating a time measurement clock, and a pulse-to-digital converter for converting the timing skew into an equivalent digital coded value after correcting for internal logic delays. The system may further include a register bank for storing the digital coded values, and a controller for generating control signals and sequences for controlling the operation of the pulse-to-digital converter and the register bank.

公开(公告)号：US07035132B2

公开(公告)日：2006-04-25

申请号：US10426004

申请日：2003-04-29

Applicant: Vivek Nautiyal ,  Ashish Kumar

Inventor： Vivek Nautiyal ,  Ashish Kumar

IPC: G11C11/00

CPC classification number: G11C7/18 ,  G11C8/14

Abstract: An improved multi-wordline memory architecture providing decreased bitline coupling to increase speed and reduce power consumption including an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.

Abstract translation: 一种改进的多字线存储器架构，其提供减少的位线耦合以增加速度并降低功耗，包括用于将相邻位单元连接到不同字线的交错布置，耦合到用于共享相邻位单元的位线的复用布置。

公开(公告)号：US20060075012A1

公开(公告)日：2006-04-06

申请号：US11238123

申请日：2005-09-28

Applicant: Deboleena Minz ,  Kailash Digari

Inventor： Deboleena Minz ,  Kailash Digari

IPC: G06F7/38

CPC classification number: G06F7/57 ,  G06F15/7867

Abstract: An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these blocks with the help of dedicated DSP lines is provided, which leads to a very simple and proficient implementation of n-stage MAC operations.

Abstract translation: 使用一个或多个计算块，每个块具有乘法器，累加器和多路复用器的现场可编程门阵列（FPGA）中的DSP功能的有效实现。 该结构以快速和高度紧凑的方式实现了大多数常见DSP方程。 提供了一种利用专用DSP线路级联这些块的新颖方法，这导致了n阶段MAC操作的非常简单和精通的实现。

公开(公告)号：US20060034132A1

公开(公告)日：2006-02-16

申请号：US11195337

申请日：2005-08-02

Applicant: Seema Jain

Inventor： Seema Jain

IPC: G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/413

Abstract: An improved synchronous SRAM capable of faster read-modify-write cycle time using separate input and output terminals. It describes the circuitry for performing a RMW operation in a memory module at high frequency in a nanometer technology. A byte write enable bus is incorporated into the device so as to provide the flexibility of modification and correction at selective columns, keeping rest of the columns unaltered. The termination of read operation and the triggering of write operation is done by the activation of same signal. Also described is the provision for tuning the circuitry for triggering write operation depending on the time taken by the controller to modify and revise the read-out data.