公开(公告)号：US20220308645A1

公开(公告)日：2022-09-29

申请号：US17702529

申请日：2022-03-23

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Roberto COLOMBO ,  Nicolas Bernard GROSSIER

IPC: G06F1/24

Abstract: A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down. During the software runtime phase, the first circuitry activate a weak pull-down for implementing a bidirectional reset terminal or activates a weak pull-up resistance for implementing a reset output terminal, and the second circuitry activates a weak pull-up for implementing a reset input terminal or activates a strong pull-up for implementing a reset output terminal.

公开(公告)号：US20220308545A1

公开(公告)日：2022-09-29

申请号：US17704675

申请日：2022-03-25

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH

Inventor： Rosario MARTORANA ,  Mose' Alessandro PERNICE ,  Roberto COLOMBO

IPC: G05B19/042

Abstract: A set of configuration memory locations store configuration data for a microcontroller unit. A hardware monitoring module is coupled by an interconnection bus to the configuration memory locations. The hardware monitoring module reads from an instruction memory a command including an address of a target memory location in the set of configuration memory locations. Data is read from the target memory location corresponding to the address read and a checksum value is computed as a function of the data that is read from the target memory location. The computed checksum value is then compared to a respective expected checksum value stored in a checksum storage unit. An alarm signal is triggered in response to a mismatch detected between the computed checksum value and the respective expected checksum value.

公开(公告)号：US11281514B2

公开(公告)日：2022-03-22

申请号：US16693103

申请日：2019-11-22

Applicant: STMicroelectronics Application GmbH

Inventor： Roberto Colombo

IPC: G06F13/42 ,  G06F11/07 ,  G06F1/10 ,  G06F1/12

Abstract: A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.

公开(公告)号：US11093658B2

公开(公告)日：2021-08-17

申请号：US15975460

申请日：2018-05-09

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio

IPC: G06F21/83 ,  G06F21/64 ,  G06F12/02 ,  G06F9/38 ,  G06F9/445 ,  H04L9/32 ,  G06F21/57 ,  G09C1/00 ,  G06F21/74 ,  H04W12/106 ,  H04L29/06 ,  H04W4/40 ,  H04W12/03 ,  H04W12/40

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

公开(公告)号：US11057194B2

公开(公告)日：2021-07-06

申请号：US16022033

申请日：2018-06-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Roberto Colombo ,  Guido Marco Bertoni ,  William Orlando ,  Roberta Vittimani

IPC: H04L9/08 ,  G06F13/36 ,  H04L9/14 ,  H04L9/32

Abstract: A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.

公开(公告)号：US10740267B1

公开(公告)日：2020-08-11

申请号：US16503243

申请日：2019-07-03

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Nirav Prashantkumar Trivedi ,  Sandip Atal ,  Rolf Nandlinger

IPC: G06F13/00 ,  G06F13/28 ,  H03M1/38 ,  H03M1/12

Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

公开(公告)号：US10375774B2

公开(公告)日：2019-08-06

申请号：US15216561

申请日：2016-07-21

Applicant: STMicroelectronics S.r.l ,  STMicroelectronics Application GMBH

Inventor： Manuel Gaertner ,  Sergio Lecce ,  Giovanni Luca Torrisi

IPC: H05B33/08 ,  B60Q1/14

Abstract: An integrated device for driving a lighting load, such as a LED, has a first memory element, configured to store a nominal duty-cycle at a nominal supply voltage. An actual voltage acquisition element is configured to detect an actual supply voltage. A processing unit is coupled to the first memory element and to the actual voltage acquisition element and configured to calculate a voltage compensated duty-cycle. A driver unit is coupled to the processing unit and is configured to be supplied according to the voltage compensated duty-cycle.

公开(公告)号：US09992916B2

公开(公告)日：2018-06-05

申请号：US14595391

申请日：2015-01-13

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Giovanni Luca Torrisi ,  Domenico Massimo Porto ,  Sergio Lecce ,  Manuel Gaertner

IPC: H01H35/00 ,  H01H35/14 ,  H01H37/00 ,  H01H47/24 ,  H01H47/26 ,  H05K7/20 ,  H01L23/34 ,  H03K17/08

CPC classification number: H05K7/20945 ,  H01L23/34 ,  H01L2924/0002 ,  H03K2017/0806 ,  Y10T307/773 ,  H01L2924/00

Abstract: A thermal control process for an electronic power device including a multi-junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.

公开(公告)号：US09606611B2

公开(公告)日：2017-03-28

申请号：US14591779

申请日：2015-01-07

Applicant: STMicroelectronics Application GmbH

Inventor： Fred Rennig

IPC: G06F1/26 ,  G06F1/32 ,  H04L12/403

CPC classification number: G06F1/3243 ,  G06F1/3209 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3293 ,  H04L12/403 ,  Y02D10/10

Abstract: A bus microcontroller includes a processor circuit having at least one unit designed for performing one or more functions due to a bus command via a communication bus, a power control circuit adapted to be coupled to a transmitter-receiver circuit for receiving bus messages via the communication bus, and a means for placing at least part of the processor circuit into a reduced-power operating mode without placing the entire processor circuit into the reduced-power operating mode. The power control circuit is designed to evaluate incoming bus messages with respect to an activation bus message containing information on activating at least part of the processor circuit, and to output a corresponding activation control signal. The bus microcontroller also includes means for activating at least a part of the processor circuit that is placed in a reduced-power operating mode, in response to output of an activation control signal of the power control circuit.

公开(公告)号：US08710801B2

公开(公告)日：2014-04-29

申请号：US13242649

申请日：2011-09-23

Applicant: Reiner Schwartz

Inventor： Reiner Schwartz

IPC: H01M10/44 ,  H01M10/46

CPC classification number: H02J7/0026 ,  H02J7/0016 ,  H02J2007/0037 ,  H02J2007/004 ,  Y02T10/7055

Abstract: A battery includes a battery module that includes a plurality of submodules electrically connected in series. Each submodule comprises first and second submodule terminals and a cell. At least one submodule in each battery module is a switchable submodule comprising a submodule switching circuit. The submodule switching circuit is switchable between a first state and a second state. The submodule switching circuit electrically connects the cell of the switchable submodule between the first and second submodule terminals when the submodule switching circuit is in the first state. The submodule switching circuit provides an electrical bypass connection between the first and second submodule terminals and the cell of the switchable submodule is electrically disconnected from at least one of the first and second submodule terminals when the switching circuit is in the second state. The battery further comprises a control unit for operating the switching circuit of each module.

Abstract translation: 电池包括电池模块，其包括串联电连接的多个子模块。 每个子模块包括第一和第二子模块终端和一个单元。 每个电池模块中的至少一个子模块是包括子模块切换电路的可切换子模块。 子模块切换电路可在第一状态和第二状态之间切换。 当子模块切换电路处于第一状态时，子模块切换电路将可切换子模块的单元电连接在第一和第二子模块端子之间。 子模块切换电路在第一和第二子模块终端之间提供电旁路连接，并且当开关电路处于第二状态时，可切换子模块的单元与第一和第二子模块端子中的至少一个电气断开。 电池还包括用于操作每个模块的开关电路的控制单元。