公开(公告)号：US06743730B1

公开(公告)日：2004-06-01

申请号：US09671201

申请日：2000-09-28

Applicant: Michiaki Sano

Inventor： Michiaki Sano

IPC: H01L21302

CPC classification number: H01L21/02063 ,  G03F7/427 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76807

Abstract: A plasma processing method that makes it possible to remove a photoresist film and fence portion while maintaining a specific shape of the opening is provided. After a wafer W is placed on a lower electrode 106 provided inside a processing chamber 102 of an ashing apparatus 100, power with its frequency set at 60 MHz and its level set at 1 kW and power with its frequency set at 2 MHz and its level set at 250 W are respectively applied to an upper electrode 122 and the lower electrode 106. A processing gas induced into the processing chamber 102 is raised to plasma, a photoresist film 208 at the wafer W is ashed and, at the same time, fence portion 214 formed around the opening of a via hole 210 during the etching process is removed. The level of the power applied to the lower electrode 106 is set equal to or lower than 10 W before the photoresist film 208 is completely removed. As a result, the energy level of the ions induced into the wafer W becomes reduced, so that the photoresist film 208 is ashed without grinding shoulders 210a and 212a of the via hole 210 and groove 212 at the SiO2 film.

Abstract translation: 提供了一种等离子体处理方法，其可以在保持开口的特定形状的同时去除光致抗蚀剂膜和栅栏部分。 将晶片W放置在设置在灰化装置100的处理室102内的下部电极106上，其频率设定为60MHz，其电平设定为1kW，功率设定为2MHz，功率为2MHz 分别施加到上部电极122和下部电极106.将处理室102中引入的处理气体升高到等离子体，晶片W上的光致抗蚀剂膜208被灰化，同时，栅栏 去除在蚀刻过程中围绕通孔210的开口形成的部分214。 在光致抗蚀剂膜208被完全去除之前，施加到下电极106的功率的电平设定为等于或低于10W。 结果，导致晶片W的离子的能级降低，使得光致抗蚀剂膜208灰化而没有在SiO 2膜上通孔210和凹槽212的磨肩210a和212a。

公开(公告)号：US20040099284A1

公开(公告)日：2004-05-27

申请号：US10614244

申请日：2003-07-08

Inventor： Nobuhiro Miki ,  Takahisa Nitta

IPC: B08B003/00 ,  B08B007/00 ,  G03F007/40 ,  B08B003/12 ,  G03F007/42

CPC classification number: H01L21/6715 ,  B08B3/00 ,  B08B3/02 ,  B08B7/0057 ,  B08B2203/0288 ,  B08B2230/01 ,  G03F7/422 ,  G03F7/427 ,  Y10T156/11 ,  Y10T156/1116 ,  Y10T156/1121

Abstract: A line slit nozzle for spraying steam is disposed along a diameter of a resist film. Steam containing a mist is sprayed onto a surface of the resist film. The film is thereby peeled off and removed. By using a change in physical properties (swelling, etc.) of the resist film by water, the film is easily and surely peeled off. Breakaway from much resources/energy consumption type techniques is realized. In other words, realized are environment-symbiosis type techniques by which resist films can be removed independently of the quantity of energy and kinds of chemical solvents.

Abstract translation: 沿着抗蚀剂膜的直径设置用于喷射蒸汽的线狭缝喷嘴。 含有雾的蒸汽喷涂在抗蚀膜的表面上。 由此剥离和除去膜。 通过使用水的抗蚀剂膜的物理性质（溶胀等）的变化，膜容易且可靠地剥离。 实现了大量资源/能源消耗类型技术的分离。 换句话说，实现了环境共生型技术，通过其可以独立于能量和化学溶剂的种类去除抗蚀剂膜。

公开(公告)号：US06736927B2

公开(公告)日：2004-05-18

申请号：US10167937

申请日：2002-06-10

Applicant: Albert Wang ,  Scott Baron ,  Prasad Padmanabhan ,  Gerald M. Cox

Inventor： Albert Wang ,  Scott Baron ,  Prasad Padmanabhan ,  Gerald M. Cox

IPC: H01J113

CPC classification number: G03F7/427 ,  H01L21/31138

Abstract: A system is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The system includes apparatus for loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature. At 40 Torr, the heat transfer from the chuck to the wafer is relatively fast, but still slow enough to avoid thermal shock. In the interim, the pump line is further pumped down to operating pressure (about 1 Torr) behind the isolation valve. The chamber pressure is then again reduced by opening the isolation valve, and the wafer is processed.

Abstract translation: 公开了一种用于在低压，高温半导体处理反应器中加速工件加工的系统。 该系统包括用于在大气压力下将工件装载到室中的装置，使室降至中间压力，并在中间压力下加热晶片。 然后将腔室泵送到操作压力。 优选实施例涉及单晶片等离子体灰化器，其中将晶片加载到晶片卡盘上方位置的升降销上，通过快速打开和关闭隔离阀将压力快速泵送至约40托，同时降低晶片 到加热的卡盘。 或者，可以预先处理晶片以在第一温度下去除植入的光致抗蚀剂的外壳，然后将该腔重新填充至约40托，以进一步加热以接近卡盘温度。 在40乇时，从卡盘到晶片的热传递相对较快，但仍然足够慢以避免热冲击。 在此期间，泵管线进一步被泵送到隔离阀后面的工作压力（约1乇）。 然后通过打开隔离阀再次减小腔室压力，并且处理晶片。

公开(公告)号：US20040084412A1

公开(公告)日：2004-05-06

申请号：US10638570

申请日：2003-08-11

Inventor： Carlo Waldfried ,  Orlando Escorcia ,  Qingyuan Han ,  Thomas Buckley ,  Palani Sakthivel

IPC: C23F001/00

CPC classification number: H01L21/02071 ,  G03F7/427 ,  H01J2237/3342 ,  H01L21/31138

Abstract: A substantially oxygen-free and nitrogen-free plasma ashing process for removing photoresist in the presence of a low k material from a semiconductor substrate includes forming reactive species by exposing a plasma gas composition to an energy source to form plasma. The plasma gas composition is substantially free from oxygen-bearing and nitrogen-bearing gases. The plasma selectively removes the photoresist from the underlying substrate containing low k material by exposing the photoresist to substantially oxygen and nitrogen free reactive species. The process can be used with carbon containing low k dielectric materials.

Abstract translation: 在半导体衬底存在低k材料的情况下，基本上无氧的无氮等离子体灰化处理用于去除光致抗蚀剂包括通过将等离子体气体组合物暴露于能量源形成等离子体来形成反应性物质。 等离子体气体组成基本上不含氧气和含氮气体。 通过将光致抗蚀剂暴露于基本上无氧和无氮的反应性物质，等离子体通过含有低k材料的下面的基底选择性地除去光致抗蚀剂。 该方法可与含碳低k电介质材料一起使用。

公开(公告)号：US20040081923A1

公开(公告)日：2004-04-29

申请号：US10370441

申请日：2003-02-20

Applicant: Nanya Technology Corporation

Inventor： Yuan-Hsun Wu ,  Teng-Yen Huang ,  Wen-Bin Wu ,  Yi-Nan Chen

IPC: G03F007/36

CPC classification number: G03F7/427 ,  H01L21/0276 ,  H01L21/31138

Abstract: A method of preventing repeated collapse in a reworked photoresist layer. First, oxygen-containing plasma is applied to remove a collapsed photoresist. Because the plasma containing oxygen reacts with a bottom anti-reflect layer comprising SiOxNy, some acids are produced on the bottom anti-reflect layer, resulting in undercutting in a subsequently reworked photoresist. Next, an alkaline solution treatment is performed on the anti-reflect layer after the collapsed photoresist layer is removed. Finally, the reworked photoresist with is formed on the anti-reflect layer, without undercutting.

Abstract translation: 防止再加工的光致抗蚀剂层中的重复塌陷的方法。 首先，施加含氧等离子体以除去塌陷的光致抗蚀剂。 因为含有氧的等离子体与包含SiO x N y的底部反射层反应，所以在底部反射层上产生一些酸，从而在随后的再加工光致抗蚀剂中进行底切。 接下来，在去除塌陷的光致抗蚀剂层之后，在抗反射层上进行碱性溶液处理。 最后，在反射层上形成返工光致抗蚀剂，而没有底切。

公开(公告)号：US06716303B1

公开(公告)日：2004-04-06

申请号：US09689616

申请日：2000-10-13

Applicant: Tuqiang Ni ,  Wenli Collison ,  David Hemker ,  Lumin Li

Inventor： Tuqiang Ni ,  Wenli Collison ,  David Hemker ,  Lumin Li

IPC: C23F100

CPC classification number: H01J37/321 ,  C23F4/00 ,  G03F7/427

Abstract: A vacuum plasma processor includes a roof structure including a dielectric window carrying (1) a semiconductor plate having a high electric conductivity so it functions as an electrode, (2) a hollow coil and (3) at least one electric shield. The shield, coil and semiconductor plate are positioned to prevent substantial coil generated electric field components from being incident on the semiconductor plate. During a first interval the coil produces an RF electromagnetic field that results in a plasma that strips photoresist from a semiconductor wafer. During a second interval the semiconductor plate and another electrode produce an RF electromagnetic field that results in a plasma that etches electric layers, underlayers and photoresist layers from the wafer.

公开(公告)号：US20040018742A1

公开(公告)日：2004-01-29

申请号：US10379980

申请日：2003-03-04

Applicant: Applied Materials, Inc.

Inventor： Jim Zhongyi He ,  Meihua Shen ,  Hong Du ,  Scott M. Williams

IPC: H01L021/302 ,  H01L021/461

CPC classification number: G03F7/405 ,  G03F7/094 ,  G03F7/427 ,  H01L21/0274 ,  H01L21/31138

Abstract: The present invention includes a method for patterning a bilayer resist having a patterned upper resist layer over a lower resist layer formed on a substrate. In one embodiment of the present invention, the method includes an optional upper resist layer trimming step, an upper resist layer treatment step, and a lower resist layer etching step. In the upper resist layer trimming step, the upper resist layer is trimmed in a plasma of a first process gas. In the upper resist layer treatment step, the upper resist layer is treated in a plasma of a second process gas to increase its etch resistance during the subsequent lower resist layer etching step. In the lower resist etching step, the lower resist layer is etched in a plasma of a third process gas, using the upper resist layer as a mask.

Abstract translation: 本发明包括在形成在基板上的下抗蚀剂层上形成图案化的上抗蚀剂层的双层抗蚀剂图案化方法。 在本发明的一个实施例中，该方法包括可选的上抗蚀剂层修整步骤，上抗蚀剂层处理步骤和下抗蚀剂层蚀刻步骤。 在上抗蚀剂层修整步骤中，在第一工艺气体的等离子体中修整上抗蚀剂层。 在上抗蚀剂层处理步骤中，在第二处理气体的等离子体中处理上抗蚀剂层，以在随后的较低抗蚀剂层蚀刻步骤期间增加其耐蚀刻性。 在较低抗蚀剂蚀刻步骤中，使用上抗蚀剂层作为掩模，在第三处理气体的等离子体中蚀刻下抗蚀剂层。

公开(公告)号：US06667244B1

公开(公告)日：2003-12-23

申请号：US09534657

申请日：2000-03-24

Applicant: Gerald M. Cox ,  John Kevin Donoghue ,  Kristel Van Baekel ,  Chan-Yun Lee

Inventor： Gerald M. Cox ,  John Kevin Donoghue ,  Kristel Van Baekel ,  Chan-Yun Lee

IPC: H01L21311

CPC classification number: H01L21/02063 ,  C01B5/00 ,  G03F7/40 ,  G03F7/427 ,  H01L21/31138

Abstract: A method for removing organic and inorganic residues or polymers from the surface of semiconductor devices, with a combination of etchant gasses including water vapor generated using a catalytic moisture generator or CMG. The water vapor is generated by introducing O2 and an H2 containing forming gas including hydrogen and at least one dilutant gas into the CMG. The water vapor from the CMG is introduced into a reaction chamber with other etchant gasses to treat the surface of a semiconductor device placed within. The flow rate of water vapor out of the CMG and into the reaction chamber may be controlled by controlling the flow rate of the H2 containing forming gas and the flow rate of the O2 gas into the CMG.

Abstract translation: 一种从半导体器件表面去除有机和无机残留物或聚合物的方法，其中包括使用催化水分发生器或CMG产生的包括水蒸气的蚀刻气体的组合。 通过将O 2和含H 2的形成气体（包括氢气和至少一种稀释气体）引入到CMG中来产生水蒸气。 将来自CMG的水蒸汽引入到具有其它蚀刻气体的反应室中以处理放置在其中的半导体器件的表面。 可以通过控制含H 2成形气体的流量和将O2气体流入CMG来控制从CMG流出并进入反应室的水蒸气流量。

公开(公告)号：US06638875B2

公开(公告)日：2003-10-28

申请号：US09876318

申请日：2001-06-07

Applicant: Qingyan Han ,  Ivan Berry ,  Palani Sakthivel ,  Ricky Ruffin ,  Mahmoud Dahimene

Inventor： Qingyan Han ,  Ivan Berry ,  Palani Sakthivel ,  Ricky Ruffin ,  Mahmoud Dahimene

IPC: H01L21302

CPC classification number: H01L21/02071 ,  G03F7/427 ,  H01J37/32192 ,  H01J37/32357 ,  H01J2237/3342 ,  H01L21/02063 ,  H01L21/31138 ,  H01L21/76813 ,  Y10S438/963

Abstract: A method for stripping photoresist and/or removing post etch residues from an exposed low k dielectric layer of a semiconductor wafer in the presence or absence of copper. The method comprises creating an oxygen free plasma by subjecting an oxygen free gas to an energy source to generate the plasma having electrically neutral and charged particles. The charged particles are then selectively removed from the plasma. The electrically neutral particles react with the photoresist and/or post etch residues to form volatile gases which are then removed from the wafer by a gas stream. The oxygen free, plasma gas composition for stripping photoresist and/or post etch residues comprises a hydrogen bearing gas and a fluorine bearing wherein the fluorine bearing gas is less than about 10 percent by volume of the total gas composition.

Abstract translation: 在存在或不存在铜时，从半导体晶片的暴露的低k电介质层剥离光刻胶和/或去除后蚀刻残留物的方法。 该方法包括通过使无氧气体经受能量源产生具有电中性和带电粒子的等离子体来产生无氧等离子体。 然后将带电粒子从等离子体中选择性地除去。 电中性颗粒与光致抗蚀剂和/或后蚀刻残余物反应以形成挥发性气体，然后通过气流从晶片中除去。 用于剥离光致抗蚀剂和/或后蚀刻残余物的无氧等离子体气体组合物包括含氢气体和氟轴承，其中含氟气体小于总气体组成的约10体积％。

公开(公告)号：US20030109393A1

公开(公告)日：2003-06-12

申请号：US10218014

申请日：2002-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dong Cho

IPC: C11D001/00

CPC classification number: H01L21/02071 ,  G03F7/427 ,  H01L21/31138

Abstract: A method for ashing a semiconductor device is provided. In the method, the semiconductor substrate, on which a metal interconnection and a photoresist pattern are formed, is processed using H2O, and then, by using a mixture of O2, N2, and H2O. The process is performed at least twice repeatedly. As a result, corrosion of the metal interconnection is inhibited and a bridge caused by conductive polymer is prevented.

Abstract translation: 提供了一种用于灰化半导体器件的方法。 在该方法中，使用H 2 O处理其上形成金属互连和光致抗蚀剂图案的半导体衬底，然后通过使用O 2，N 2和H 2 O的混合物进行处理。 该过程至少执行两次。 结果，金属互连的腐蚀被抑制，并且防止由导电聚合物引起的桥。