公开(公告)号：US20220068878A1

公开(公告)日：2022-03-03

申请号：US17033945

申请日：2020-09-28

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Chen-Liang Ma ,  Zih-Song Wang

IPC分类号： H01L25/065 ,  H01L27/11558 ,  H01L27/11563 ,  H01L27/24

摘要： A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.

公开(公告)号：US11251277B2

公开(公告)日：2022-02-15

申请号：US17019557

申请日：2020-09-14

申请人： BECSIS, LLC

发明人： Nicholas Boruta ,  Michael Boruta

IPC分类号： H01L21/8238 ,  H01L29/792 ,  H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11563 ,  H01L29/66 ,  H01L29/861

摘要： An electrode having an embedded charge contains a substrate, a first electronic charge trap defined at the interface of a first insulating layer and a second insulating layer; and a first conductive layer disposed on the first electronic charge trap; wherein the first conductive layer contains a conductive material configured to permit an external electric field to penetrate the electrode from the first electronic charge trap; and wherein the first insulating layer is not the same as the second insulating layer.

公开(公告)号：US10985013B2

公开(公告)日：2021-04-20

申请号：US16430882

申请日：2019-06-04

申请人： Versum Materials US, LLC

发明人： Jianheng Li ,  Robert G. Ridgeway ,  Xinjian Lei ,  Raymond N. Vrtis ,  Bing Han ,  Madhukar B. Rao

IPC分类号： H01L21/02 ,  C23C16/34 ,  C23C16/40 ,  C01B21/087 ,  C07F7/10 ,  H01L27/11517 ,  H01L27/11556 ,  H01L27/11563 ,  H01L27/11582

摘要： Described herein is an apparatus comprising a plurality of silicon-containing layers wherein the silicon-containing layers are selected from a silicon oxide and a silicon nitride layer or film. Also described herein are methods for forming the apparatus to be used, for example, as 3D vertical NAND flash memory stacks. In one particular aspect or the apparatus, the silicon oxide layer comprises slightly compressive stress and good thermal stability. In this or other aspects of the apparatus, the silicon nitride layer comprises slightly tensile stress and less than 300 MPa stress change after up to about 800° C. thermal treatment. In this or other aspects of the apparatus, the silicon nitride layer etches much faster than the silicon oxide layer in hot H3PO4, showing good etch selectivity.

公开(公告)号：US10818691B2

公开(公告)日：2020-10-27

申请号：US16569951

申请日：2019-09-13

申请人： Toshiba Memory Corporation

发明人： Toshifumi Minami ,  Atsuhiro Sato ,  Keisuke Yonehama ,  Yasuyuki Baba ,  Hiroshi Shinohara ,  Hideyuki Kamata ,  Teppei Higashitsuji

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11563 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11551

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US10720440B2

公开(公告)日：2020-07-21

申请号：US15927914

申请日：2018-03-21

申请人： United Microelectronics Corp.

发明人： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/78 ,  H01L27/11573 ,  H01L27/11543 ,  H01L27/11563 ,  H01L21/28 ,  H01L29/788

摘要： A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US10714498B2

公开(公告)日：2020-07-14

申请号：US16294150

申请日：2019-03-06

申请人： Toshiba Memory Corporation

发明人： Harumi Seki ,  Yuichiro Mitani ,  Takamitsu Ishihara

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  G11C8/14 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11563

摘要： According to one embodiment, a semiconductor memory device includes: a first interconnect layer; a second interconnect layer adjacent to the first interconnect layer; a semiconductor layer between the first and second interconnect layers; a first charge storage layer between the first interconnect layer and the semiconductor layer; and a second charge storage layer between the second interconnect layer and the semiconductor layer. A first distance between the first and second interconnect layers is shorter than a second distance between the first and second charge storage layers.

公开(公告)号：US20190341395A1

公开(公告)日：2019-11-07

申请号：US16515352

申请日：2019-07-18

申请人： Renesas Electronics Corporation

发明人： Tadashi YAMAGUCHI

IPC分类号： H01L27/11563 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L29/792 ,  H01L29/45

摘要： A method for manufacturing a semiconductor device to provide a Metal Insulator Semiconductor Field Effect Transistor (MISFET) in a first region of a semiconductor substrate includes forming a first gate insulating film on the semiconductor substrate in the first region, forming a first gate electrode containing silicon on the first gate insulating film, forming first impurity regions inside the semiconductor substrate so as to sandwich the first gate electrode in the first region, the first impurity regions configuring a part of a first source region and a part of a first drain region, forming a first silicide layer on the first impurity region, forming a first insulating film on the semiconductor substrate so as to cover the first gate electrode and the first silicide layer, polishing the first insulating film so as to expose the first gate electrode, and forming a second silicide layer on the first gate electrode.

公开(公告)号：US20190319039A1

公开(公告)日：2019-10-17

申请号：US16454914

申请日：2019-06-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hongsoo Kim ,  Hyunmog Park ,  Joongshik Shin

IPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11575 ,  H01L27/06 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11563 ,  H01L21/822 ,  H01L27/1157

摘要： A vertical memory device structure can include a vertical channel structure that vertically penetrates through an upper structure and a lower structure of a stack structure in a cell array region of the device. The vertical channel structure can have a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the lower structure. A vertical dummy structure can vertically penetrate through a staircase structure that is defined by the upper structure and the lower structure in a connection region of the device, and the vertical dummy structure can have a side wall with a planar profile at the level where the upper structure meets the lower structure.

公开(公告)号：US10418373B2

公开(公告)日：2019-09-17

申请号：US16189319

申请日：2018-11-13

申请人： LONGITUDE FLASH MEMORY SOLUTIONS LTD.

发明人： Krishnaswamy Ramkumar

IPC分类号： H01L21/8234 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/167 ,  H01L29/792 ,  H01L21/02 ,  H01L27/11563 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11573 ,  H01L21/28

摘要： A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

公开(公告)号：US20190198329A1

公开(公告)日：2019-06-27

申请号：US16240366

申请日：2019-01-04

申请人： Cypress Semiconductor Corporation

发明人： Fredrick B. Jenne ,  Krishnaswamy Ramkumar

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/02 ,  G11C16/04 ,  H01L29/792 ,  H01L29/51 ,  H01L27/11563

摘要： A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.