公开(公告)号：US20220020744A1

公开(公告)日：2022-01-20

申请号：US17447506

申请日：2021-09-13

申请人： Tokyo Electron Limited

发明人： Mark I. Gardner ,  H. Jim Fulford

IPC分类号： H01L27/092 ,  H01L29/786 ,  H01L29/161 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/24

摘要： In a method for forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers with a first bandgap value and one or more second nano layers with a second bandgap value. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks such that the one or more first nano layers are separated into first nano-channels, and the one or more second nano layers are separated into second nano-channels. The intermediate layers are recessed so that the first nano-channels and the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Top source/drain (S/D) regions are formed in the trenches and in direct contact with the first nano-channels. Bottom source/drain (S/D) regions are formed in the trenches and in direct contact with the second nano-channels.

公开(公告)号：US20210408258A1

公开(公告)日：2021-12-30

申请号：US16912118

申请日：2020-06-25

申请人： Intel Corporation

发明人： Dan S. LAVRIC ,  Glenn A. GLASS ,  Thomas T. TROEGER ,  Suresh VISHWANATH ,  Jitendra Kumar JHA ,  John F. RICHARDS ,  Anand S. MURTHY ,  Srijit MUKHERJEE

IPC分类号： H01L29/45 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66

摘要： Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US11205702B2

公开(公告)日：2021-12-21

申请号：US16086275

申请日：2017-03-31

申请人： Soitec

发明人： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

IPC分类号： H01L29/161 ,  H01L23/00 ,  H01L21/306

摘要： A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

公开(公告)号：US20210391450A1

公开(公告)日：2021-12-16

申请号：US16902170

申请日：2020-06-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shahaji B. MORE ,  Chien LIN ,  Cheng-Han LEE ,  Shih-Chieh CHANG ,  Shu KUAN

IPC分类号： H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/161

摘要： In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

公开(公告)号：US20210391386A1

公开(公告)日：2021-12-16

申请号：US16898234

申请日：2020-06-10

申请人： SPIN (assignment for benefit of creditors), LLC

发明人： Dafna Beery ,  Peter Cuevas ,  Amitay Levi ,  Andrew J. Walker

IPC分类号： H01L27/24 ,  H01L27/22 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/24 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/443 ,  H01L29/66

摘要： A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure can be tungsten (W). In addition, a thin layer of Ti or TiN can be formed between the metal gate layer and the first and second dielectric layers and the gate dielectric layer. The metal gate layer can be formed with or without the use of a sacrificial layer.

公开(公告)号：US11201153B2

公开(公告)日：2021-12-14

申请号：US16801904

申请日：2020-02-26

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Chun-Chen Yeh ,  Alexander Reznicek ,  Dechao Guo

IPC分类号： H01L29/161 ,  H01L29/45 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L29/165 ,  H01L29/06

摘要： Embodiments of the present invention are directed to a method for forming a complementary field effect transistor (CFET) structure having a wrap-around contact. In a non-limiting embodiment of the invention, a complementary nanosheet stack is formed over a substrate. The complementary nanosheet stack includes a first nanosheet and a second nanosheet separated by a dielectric spacer. A first sacrificial layer is formed over a source or drain (S/D) region of the first nanosheet and a second sacrificial layer is formed over a S/D region of the second nanosheet. A conductive gate is formed over channel regions of the first nanosheet and the second nanosheet. After the conductive gate is formed, the first sacrificial layer is replaced with a first wrap-around contact and the second sacrificial layer is replaced with a second wrap-around contact.

公开(公告)号：US20210359111A1

公开(公告)日：2021-11-18

申请号：US17109895

申请日：2020-12-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ya-Wen CHIU ,  Yi Che CHAN ,  Lun-Kuang TAN ,  Zheng-Yang PAN ,  Cheng-Po CHAU ,  Pin-Ju LIANG ,  Hung-Yao CHEN ,  De-Wei YU ,  Yi-Cheng LI

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/161 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8238

摘要： In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

公开(公告)号：US11177366B2

公开(公告)日：2021-11-16

申请号：US16740958

申请日：2020-01-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Alexander Reznicek ,  Takashi Ando ,  Jingyun Zhang ,  Ruilong Xie

IPC分类号： H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/161 ,  H01L29/08

摘要： A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

公开(公告)号：US11158637B2

公开(公告)日：2021-10-26

申请号：US16908215

申请日：2020-06-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Chih-Sheng Chang ,  Zhiqiang Wu

IPC分类号： H01L27/092 ,  H01L29/16 ,  H01L29/165 ,  H01L29/161 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L29/78 ,  H01L29/167 ,  H01L29/06

摘要： The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.

公开(公告)号：US20210305392A1

公开(公告)日：2021-09-30

申请号：US17304108

申请日：2021-06-14

申请人： Acorn Semi, LLC

发明人： Daniel E. Grupp ,  Daniel J. Connelly

IPC分类号： H01L29/45 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/47 ,  H01L29/66 ,  H01L29/78 ,  H01L29/80 ,  H01L29/812 ,  H01L29/872 ,  H01L21/285

摘要： An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.