公开(公告)号：US20240047341A1

公开(公告)日：2024-02-08

申请号：US17880359

申请日：2022-08-03

申请人： International Buisness Machines Corporation

发明人： Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Brent A. Anderson ,  Reinaldo Vega ,  Albert M. Chu ,  Lawrence A. Clevenger

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L23/5283 ,  H01L21/76877 ,  H01L21/76816

摘要： Interconnect designs with reduced via resistance are provided. In one aspect, an interconnect structure includes: at least a first metal line and a second metal line; and a conductive via in between the first metal line and the second metal line, wherein the conductive via has elongated dimensions along a major axis of the first metal line and along a major axis of the second metal line. Dielectric caps can be present on the first metal lines, and below and above the second metal lines. A method of forming the present interconnect structure is also provided.

公开(公告)号：US10698618B1

公开(公告)日：2020-06-30

申请号：US16365419

申请日：2019-03-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Zah Barzik ,  Lior Chen ,  Michael Keller ,  Rivka M. Matosevich

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F11/07

摘要： Methods, computing systems and computer program products implement embodiments of the present invention that include defining a plurality of failure domains for sets of storage devices in a storage facility, and defining, using the failure domains, one or more limitations for distributing data on the storage devices. Upon identifying a data distribution configuration for a software defined storage system that is compliant with the one or more limitations, the identified data distribution configuration can be presented to a user. The failure domains may include physical failure domains, logical failure domains, or a combination of physical and logical failure domains, and the limitations may include mandatory limitations or a combination of mandatory and non-mandatory limitations. In embodiments including non-mandatory limitations, the data distribution configuration may not comply with all the non-mandatory limitations, and any non-mandatory limitations that are not met can be flagged and presented to the user.

公开(公告)号：US08386350B2

公开(公告)日：2013-02-26

申请号：US11696104

申请日：2007-04-03

申请人： Gregory M. Plow ,  Farrokh E. Pourmirzaie

发明人： Gregory M. Plow ,  Farrokh E. Pourmirzaie

IPC分类号： G06Q40/00

CPC分类号： G06Q40/06 ,  G06Q50/184 ,  G06Q90/00

摘要： A system and methods for extracting value from a portfolio of assets, for example a patent portfolio, are described. By granting floating privileges described herein, a portfolio owner can extend an opportunity for obtaining an interest in selected assets from the portfolio to a client who lacks the resources to accumulate and maintain such a portfolio, in return for an annuity stream to the portfolio owner. The floating privilege can take many forms, depending on the needs of the client and the nature of the assets in the portfolio. The privilege is executed for a set of assets selected by the client and approved by the portfolio owner in accordance with a floating privilege agreement controlling the floating privilege.

摘要翻译： 描述了从资产组合中提取价值的系统和方法，例如专利组合。 通过授予本文所述的浮动特权，投资组合所有者可以扩大获得投资组合中所选资产的利益的机会，而不是资源累积和维持此类投资组合的客户，以换取投资组合所有者的年金流。 浮动特权可以采取多种形式，这取决于客户的需求和投资组合中资产的性质。 特权是由客户选定的一组资产执行，并由投资组合所有者根据控制浮动特权的浮动特权协议批准。

公开(公告)号：US08319113B2

公开(公告)日：2012-11-27

申请号：US12797244

申请日：2010-06-09

申请人： Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Nam H. Pham ,  Terence Rodrigues

发明人： Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Nam H. Pham ,  Terence Rodrigues

IPC分类号： H05K1/00 ,  H05K3/00

CPC分类号： H05K1/024 ,  H05K3/4602 ,  H05K3/4697 ,  Y10T29/49124 ,  Y10T29/49155

摘要： A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB.

摘要翻译： 一种具有降低的介质损耗的印刷电路板（PCB），包括设置在介电材料层上的导电迹线，所述介电材料层包括芯层和预浸料层，介电材料层中的一个或多个包括空气袋， PCB的总相对介电常数。

公开(公告)号：US20120167024A1

公开(公告)日：2012-06-28

申请号：US13415924

申请日：2012-03-09

申请人： JASON R. BAUMGARTNER ,  MICHAEL L. CASE ,  HARI MONY ,  VIRESH PARUTHI

发明人： JASON R. BAUMGARTNER ,  MICHAEL L. CASE ,  HARI MONY ,  VIRESH PARUTHI

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.

摘要翻译： 在验证逻辑网络设计之前，用于减小逻辑网络设计大小的方法，系统和计算机程序产品。 该方法包括消除寄存器以减小逻辑网络设计的大小; 从而增加验证过程的速度和功能，并减小逻辑网络设计的大小。 系统识别所选择的寄存器的一个或多个兼容的重新配置，其中兼容重新配置将所选择的寄存器表示为一个或多个预先存在的固定初始状态的寄存器。 利用设计不变量来改进重组。 当再进行一次重新配置时，系统将删除所选择的寄存器以减小逻辑网络设计的大小。 作为重新配置处理的结果，生成尺寸减小的逻辑网络设计。

公开(公告)号：US20110047350A1

公开(公告)日：2011-02-24

申请号：US12544541

申请日：2009-08-20

申请人： Andrew Geissler ,  Raymond J. Harrington ,  Hye-Young McCreary ,  Freeman Leigh Rawson, III ,  Malcolm Scott Ware

发明人： Andrew Geissler ,  Raymond J. Harrington ,  Hye-Young McCreary ,  Freeman Leigh Rawson, III ,  Malcolm Scott Ware

IPC分类号： G06F9/00 ,  G06F15/80

CPC分类号： G06F1/324 ,  G06F9/5061 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/22

摘要： A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range.

摘要翻译： 由多个处理节点执行的分区。 每个节点包括多个核心，每个核心都具有可设置的频率。 第一频率范围被提供给核心。 每个核心在执行识别的分区时，将其频率设置在第一个频率范围内。 从节点运行分区的内核收集频率度量。 收集的频率度量由管理程序接收和分析，管理程序确定用于分区的第二频率范围，其中第二频率范围不同于第一频率范围。 将第二频率范围提供给执行识别的分区的节点处的核心。 当核心执行识别的分区时，它们使用第二频率范围内的频率。

公开(公告)号：US20100332693A1

公开(公告)日：2010-12-30

申请号：US12494274

申请日：2009-06-30

申请人： Shmuel Ben-Yehuda ,  Leah Shalev ,  Orit Luba Wasserman ,  Ben-Ami Yassour

发明人： Shmuel Ben-Yehuda ,  Leah Shalev ,  Orit Luba Wasserman ,  Ben-Ami Yassour

IPC分类号： G06F13/28 ,  G06F12/00 ,  G06F12/10

CPC分类号： G06F12/1081

摘要： A method of address translation in a computing system providing direct memory access (DMA) by way of one or more remote memory management units (MMUs) is provided. The method comprises intercepting a request for a first DMA operation forwarded by a first device to a second device; and translating a guest address included in the request to a first address according to a mapping referencing a memory frame in a memory of the second device. A local MMU increments a first reference count indicating number of active DMA operations directed to the memory frame and a second reference count indicating number of remote MMUs that have mapped the memory frame.

摘要翻译： 提供了一种通过一个或多个远程存储器管理单元（MMU）提供直接存储器访问（DMA）的计算系统中的地址转换方法。 该方法包括拦截由第一设备转发到第二设备的第一DMA操作的请求; 以及根据引用所述第二设备的存储器中的存储器帧的映射将所述请求中包括的访客地址转换为第一地址。 本地MMU增加指示针对存储器帧的活动DMA操作数的第一参考计数和指示映射存储器帧的远程MMU的数量的第二参考计数。

公开(公告)号：US20100269119A1

公开(公告)日：2010-10-21

申请号：US12424893

申请日：2009-04-16

申请人： Ravi Kumar Arimilli ,  Piyush Chaudhary

发明人： Ravi Kumar Arimilli ,  Piyush Chaudhary

IPC分类号： G06F9/46

CPC分类号： G06F9/5011 ,  G06F9/5061

摘要： Disclosed are a method, a system and a computer program product for automatically allocating and de-allocating resources for jobs executed or processed by one or more supercomputer systems. In one or more embodiments, a supercomputing system can process multiple jobs with respective supercomputing resources. A global resource manager can automatically allocate additional resources to a first job and de-allocate resources from a second job. In one or more embodiments, the global resource manager can provide the de-allocated resources to the first job as additional supercomputing resources. In one or more embodiments, the first job can use the additional supercomputing resources to perform data analysis at a higher resolution, and the additional resources can compensate for an amount of time the higher resolution analysis would take using originally allocated supercomputing resources.

摘要翻译： 公开了一种用于为由一个或多个超级计算机系统执行或处理的作业自动分配和分配资源的方法，系统和计算机程序产品。 在一个或多个实施例中，超级计算系统可以使用相应的超级计算资源处理多个作业。 全局资源管理器可以自动为第一个作业分配额外的资源，并从第二个作业中分配资源。 在一个或多个实施例中，全局资源管理器可以将去分配的资源作为附加的超级计算资源提供给第一作业。 在一个或多个实施例中，第一作业可以使用额外的超级计算资源以更高的分辨率执行数据分析，并且附加资源可以补偿使用原始分配的超级计算资源的更高分辨率分析所花费的时间量。

公开(公告)号：US20100264731A1

公开(公告)日：2010-10-21

申请号：US12425267

申请日：2009-04-16

申请人： Ravi Kumar Arimilli ,  Edward Joseph Seminaro ,  Kevin Covi ,  Gerald J. Fahr ,  Daniel James Barus

发明人： Ravi Kumar Arimilli ,  Edward Joseph Seminaro ,  Kevin Covi ,  Gerald J. Fahr ,  Daniel James Barus

IPC分类号： H02J4/00

CPC分类号： H02J1/102 ,  Y10T307/352 ,  Y10T307/707

摘要： A power conversion, control, and distribution system includes multiple bulk power regulator (BPR) subassemblies, a bulk power distribution (BPD) subassembly, and a bulk power controller and hub (BPCH) subassembly. The BPR subassemblies are each configured to provide regulated DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the regulated DC power. The BPCH subassembly is coupled to the multiple BPR subassemblies and the BPD subassembly. The BPCH subassembly is configured to monitor and control the BPR assemblies and the BPD assembly.

摘要翻译： 电力转换，控制和分配系统包括多个大功率调节器（BPR）子组件，大容量配电（BPD）子组件和大容量功率控制器和集线器（BPCH）子组件。 BPR子组件各自配置为从交流输入功率和直流输入功率提供稳压的直流电源。 BPD子组件被配置为分配调节的直流电力。 BPCH子组件耦合到多个BPR子组件和BPD子组件。 BPCH子组件被配置为监视和控制BPR组件和BPD组件。

公开(公告)号：US20100262787A1

公开(公告)日：2010-10-14

申请号：US12421338

申请日：2009-04-09

申请人： Lakshminarayana Baba Arimilli ,  Ravi K. Arimilli ,  Jody B. Joyner ,  William J. Starke

发明人： Lakshminarayana Baba Arimilli ,  Ravi K. Arimilli ,  Jody B. Joyner ,  William J. Starke

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F12/1027 ,  G06F12/123

摘要： A technique for performing cache injection includes monitoring, at a host fabric interface, snoop responses to an address on a bus. When the snoop responses indicate a data block associated with the address is in a shared state, input/output data associated with the address on the bus is directed to a cache that includes the data block in the shared state and is located physically closer to the host fabric interface than one or more other caches that include the data block associated with the address in the shared state.

摘要翻译： 用于执行高速缓存注入的技术包括在主机结构接口处监视对总线上的地址的响应。 当窥探响应指示与地址相关联的数据块处于共享状态时，与总线上的地址相关联的输入/输出数据被引导到包括处于共享状态的数据块的高速缓存，并且物理上更靠近 主机结构接口比包括与共享状态中的地址相关联的数据块的一个或多个其他高速缓存。