公开(公告)号：US09835515B2

公开(公告)日：2017-12-05

申请号：US14511346

申请日：2014-10-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Alberto Pagani

IPC: G01L25/00 ,  G01L1/16 ,  G01L1/22 ,  G01L1/26

CPC classification number: G01L25/00 ,  G01L1/16 ,  G01L1/2206 ,  G01L1/26

Abstract: A pressure sensor is for positioning within a structure. The pressure sensor may include a pressure sensor integrated circuit (IC) having a pressure sensor circuit responsive to bending, and a transceiver circuit coupled to the pressure sensor circuit. The pressure sensor may include a support body having a recess therein coupled to the pressure sensor IC so that the pressure sensor IC bends into the recess when the pressure sensor IC is subjected to external pressure.

公开(公告)号：US20140182394A1

公开(公告)日：2014-07-03

申请号：US14108688

申请日：2013-12-17

Applicant: STMICROELETRONICS S.R.L.

Inventor： Alberto Pagani ,  Federico Giovanni Ziglioli ,  Bruno Murari

IPC: G01L1/18 ,  G01B7/16

CPC classification number: G01L1/18 ,  G01B7/18 ,  G01L1/26 ,  G01M5/0041 ,  G01M5/0083

Abstract: The integrated electronic device is for detecting a local parameter related to a force experienced in a predetermined direction within a solid structure. The device includes a semiconductor substrate having a substantially planar region that defines a plane substantially perpendicular to the predetermined direction. At least one sensor detects the local parameter at least in the predetermined direction with a piezo-resistive effect. At least one substantially planar face is arranged in a portion of the integrated electronic device, the face belonging to a inclined plane by a predetermined angle relative to the plane perpendicular to the predetermined direction, which plane is defined by the substantially planar region of the substrate. The predetermined angle is defined such as to reduce forces acting in directions other than the predetermined direction at the portion of the device around the at least one sensor.

Abstract translation: 集成电子装置用于检测与固体结构内的预定方向上经受的力有关的局部参数。 该器件包括具有限定基本上垂直于预定方向的平面的基本平坦的区域的半导体衬底。 至少一个传感器至少在预定方向上以压阻效应来检测局部参数。 至少一个基本上平坦的面布置在集成电子设备的一部分中，该面部属于倾斜平面，相对于垂直于该预定方向的平面成预定角度，该平面由基板的基本平坦的区域限定 。 预定角度被限定为在围绕该至少一个传感器的装置的部分处减小作用于除了预定方向以外的方向的力。

公开(公告)号：US20130007396A1

公开(公告)日：2013-01-03

申请号：US13531942

申请日：2012-06-25

Applicant: Francesco VARONE ,  Amedeo Veneroso

Inventor： Francesco VARONE ,  Amedeo Veneroso

IPC: G06F12/14

CPC classification number: G06F21/79 ,  G06F12/14 ,  G06F21/31 ,  G11B20/00152 ,  G11B20/0021 ,  G11B20/00695 ,  G11B2020/00057 ,  G11B2220/61

Abstract: The method is for protecting the digital contents of a solid state memory including a microprocessor. A microprocessor inserts at least an interruption during a copy or a reading of the digital contents and proceeds with the copy or reading only subsequently to a verification of a PIN. In particular, the verification provides control that the PIN is inserted manually. Also, a solid state memory includes a microprocessor programmed for inserting at least an interruption in a copy or reading of digital contents of the memory, for verifying a PIN, and for proceeding with the copy or the reading, if the PIN is inserted correctly.

Abstract translation: 该方法用于保护包含微处理器的固态存储器的数字内容。 微处理器在数字内容的复制或读取期间插入至少一个中断，然后继续复制或读取仅在PIN的验证之后。 特别地，验证提供了手动插入PIN的控制。 此外，固态存储器包括微处理器，其被编程为至少插入存储器的数字内容的复制或读取中的中断，用于验证PIN，并且如果PIN被正确插入，则进行复制或读取。

公开(公告)号：US06934102B2

公开(公告)日：2005-08-23

申请号：US10033726

申请日：2001-12-28

Applicant: Angelo Dati ,  Davide Giovenzana

Inventor： Angelo Dati ,  Davide Giovenzana

IPC: G11B20/10 ,  G11B5/09 ,  H03M7/20 ,  H04L27/10

CPC classification number: G11B20/10287 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10296

Abstract: A system provides two distinct solutions for encoding and decoding servo positioning data for a hard disk drive. A first solution includes: encoding each group of four bits of a pattern signal in a Matched Spectral Null (MSN) format through an intermediate rate 4/6 code; providing a duplicated bit for each bit of the six bit code word obtained with the previous step. A second solution includes: encoding each group of four bit of the pattern signal adding a parity check bit as an intermediate rate ⅘ code; encoding each of the five bits using the biphase map. Both solutions include subsequently: reading a servo wedge information signal using a read and write channel of the hard disk drive; and using a trellis Partial Response decoding scheme matched to the encoded word for obtaining angular and radial information for the head positioning.

Abstract translation: 系统为硬盘驱动器的伺服定位数据的编码和解码提供了两个不同的解决方案。 第一个解决方案包括：通过中间速率4/6代码以匹配光谱空（MSN）格式对每组4位模式信号进行编码; 为前一步获得的六位码字的每一位提供一个复制位。 第二个解决方案包括：对每一组四位模式信号进行编码，将奇偶校验位作为中间速率4/5代码; 使用双相图编码五位中的每一位。 这两种解决方案包括：使用硬盘驱动器的读和写通道读取伺服楔信息信号; 并且使用与编码字匹配的网格部分响应解码方案来获得头部定位的角度和径向信息。

公开(公告)号：US06061269A

公开(公告)日：2000-05-09

申请号：US613443

申请日：1996-03-04

Applicant: Livio Baldi ,  Paola Paruzzi

Inventor： Livio Baldi ,  Paola Paruzzi

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC classification number: H01L29/7885

Abstract: The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and lacking the second source diffusion.

Abstract translation: 本发明涉及一种电可编程和可擦除的非易失性存储单元，其具有传统结构，但在组分元件的导电类型中被反转，并且缺少第二源扩散。

公开(公告)号：US20080118405A1

公开(公告)日：2008-05-22

申请号：US11875755

申请日：2007-10-19

Applicant: Sabrina Conoci ,  Salvatore Sortino

Inventor： Sabrina Conoci ,  Salvatore Sortino

IPC: B01J19/00 ,  C07D211/04

CPC classification number: C07D213/30

Abstract: A bifunctional compound comprising a molecular unit (I) intercalating between nucleobases (B) of nucleic acids, an active molecular unit (AD) capable of emitting a detectable signal, and optionally a spacer unit, in which the active molecular unit (AD) is selected from amongst chemical entities having a structure such as to interact electronically with the intercalating molecular unit (I) in such a way that, during the reaction of oxidation, the reduction-oxidation potential (EI+/I) of the semicouple I+/I defined by the intercalating molecular unit (I) is lower than the reduction-oxidation potential (EB+/B) of the semicouple B+/B defined by the nucleobases (B), and in such a way that, during the reaction of reduction, the reduction-oxidation potential (EI/I−) of the semicouple I/I− defined by the intercalating molecular unit (I) is higher than the reduction-oxidation potential (EB/B−) of the semicouple B/B− defined by the nucleobases (B). Moreover the use of the compound for detecting nucleic acids, a process for its synthesis, and a system comprising the same are described.

Abstract translation: 包含嵌入核酸碱基（B）之间的分子单元（I），能够发射可检测信号的活性分子单元（AD）和任选的间隔单元的双功能化合物，其中活性分子单元（AD）为 选自具有如下结构的化学实体，其结构使得与插层分子单元（I）以电子方式相互作用，使得在氧化反应期间，所述半导体I + / I的还原氧化电位（EI + / I）被定义 插层分子单元（I）的含量低于由核碱基（B）定义的半组分B + / B的还原 - 氧化电位（EB + / B），并且在还原反应期间还原 由插入分子单元（I）定义的半配偶I / I的氧化电位（EI / I）高于由核碱基限定的半组分B / B-的还原 - 氧化电位（EB / B-） （B）。 此外，描述了化合物用于检测核酸的用途，其合成方法和包含其的体系。

公开(公告)号：US6031416A

公开(公告)日：2000-02-29

申请号：US67127

申请日：1998-04-27

Applicant: Andrea Baschirotto ,  Ugo Baschirotto ,  Guido Brasca ,  Rinaldo Castello

Inventor： Andrea Baschirotto ,  Ugo Baschirotto ,  Guido Brasca ,  Rinaldo Castello

IPC: H03H11/04 ,  H03K5/00

CPC classification number: H03H11/04

Abstract: A CMOS elementary cell of the first order for time-continuous analog filters with non-linearity compensation, is connected between a first supply voltage reference and a second voltage reference. The cell is of a type which comprises at least a first MOS transistor having its conduction terminals connected to the first supply voltage reference and to an output terminal, and having a control terminal connected to an input terminal of the first order CMOS elementary cell. The cell further comprises a second MOS transistor in diode configuration, and an equivalent capacitor, both connected to the output terminal of the first order CMOS elementary cell. The second, diode-connected MOS transistor and the equivalent capacitor act as a load for the first MOS transistor. The first MOS transistor operates as a drive transistor operatively tied to an input voltage signal being supplied to the input terminal of the first order CMOS elementary cell. A second order filter CMOS elementary cell is similarly connected.

Abstract translation: 具有非线性补偿的时间连续模拟滤波器的第一阶CMOS元件连接在第一电源电压基准和第二参考电压之间。 电池是至少包括其导通端子连接到第一电源电压基准的第一MOS晶体管和输出端子，并且具有连接到第一级CMOS基本单元的输入端子的控制端子的类型。 电池还包括二极管配置的第二MOS晶体管和等效电容器，两者均连接到一阶CMOS元件单元的输出端子。 第二个二极管连接的MOS晶体管和等效电容器用作第一MOS晶体管的负载。 第一MOS晶体管作为驱动晶体管工作，该驱动晶体管可操作地连接到被提供给第一阶CMOS元件单元的输入端的输入电压信号。 类似地连接二阶滤波器CMOS单元。

公开(公告)号：US6016271A

公开(公告)日：2000-01-18

申请号：US141250

申请日：1998-08-27

Applicant: Paolo Rolandi ,  Roberto Gastaldi ,  Cristiano Calligaro

Inventor： Paolo Rolandi ,  Roberto Gastaldi ,  Cristiano Calligaro

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/30 ,  G11C16/04

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/30 ,  G11C2211/5634 ,  G11C29/00 ,  G11C8/14

Abstract: A circuit generates a regulated voltage, in particular for gate terminals of non-volatile memory cells of the floating gate type. The circuit includes a generator circuit adapted to generate an unregulated voltage on its output. A comparator circuit is coupled to the output of the generator circuit including a reference element including a non-volatile memory cell of the floating gate type and adapted to output an error signal tied to the difference between the unregulated voltage and the threshold voltage of the cell. A regulator circuit is coupled to the output of the comparator circuit and is operative to regulate the unregulated voltage based on the value of the error signal. The regulated voltage is made programmable and tied to the parameters of the memory cell.

Abstract translation: 电路产生调节电压，特别是对浮栅型非易失性存储单元的栅极端子。 电路包括适于在其输出上产生未调节电压的发生器电路。 比较器电路耦合到发生器电路的输出端，该输出包括一个参考元件，该参考元件包括一个浮动型的非易失性存储单元，并且适于输出一个与非稳态电压和该单元的阈值电压之间的差值相关的误差信号 。 调节器电路耦合到比较器电路的输出，并且可操作以基于误差信号的值来调节未调节的电压。 调节电压是可编程的，并且与存储器单元的参数相关联。

公开(公告)号：US10771042B2

公开(公告)日：2020-09-08

申请号：US15976611

申请日：2018-05-10

Applicant: STMicroelectronics S.r.l.

Inventor： Gabriele Gattere ,  Lorenzo Corso ,  Alessandro Tocchio ,  Carlo Valzasina

IPC: H03H9/02 ,  H03H9/24 ,  H03H3/007 ,  H03H9/46 ,  H03H9/05

Abstract: A microelectromechanical device having a mobile structure including mobile arms formed from a composite material and having a fixed structure including fixed arms capacitively coupled to the mobile arms. The composite material includes core regions of insulating material and a silicon coating.

公开(公告)号：US09330211B2

公开(公告)日：2016-05-03

申请号：US13230135

申请日：2011-09-12

Applicant: Francesco Papariello ,  Giuseppe Desoli

Inventor： Francesco Papariello ,  Giuseppe Desoli

IPC: G06F9/44 ,  G06F13/10 ,  G06F13/12 ,  G06F9/45 ,  G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5022 ,  G06F9/455 ,  G06F17/5009 ,  G06F17/5036

Abstract: An embodiment of a simulation tool includes a path determiner and a simulator. The path determiner is configured to identify a first communication path between first and second devices of a system, and the simulator is configured to simulate a routing of a first item from one of the first and second devices to the other of the first and second devices via the identified path. The path determiner may also be configured to identify the communication path before the simulator simulates the routing of the item, or to identify the communication path while the simulator is inactive.

Abstract translation: 模拟工具的实施例包括路径确定器和模拟器。 路径确定器被配置为识别系统的第一和第二设备之间的第一通信路径，并且模拟器被配置为模拟第一项目从第一和第二设备中的一个到第一和第二设备中的另一个的路由 通过识别的路径。 路径确定器还可以被配置为在模拟器模拟项目的路由之前识别通信路径，或者在模拟器不活动时识别通信路径。