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公开(公告)号：US20240264225A1
公开(公告)日：2024-08-08
申请号：US18641453
申请日：2024-04-22
发明人： Yasunobu Torii
CPC分类号： G01R31/2891 , G01B7/003 , G01R1/07307
摘要： A probe position monitoring structure includes a first common line, a second common line, a contact portion configured, and a reference zigzag structure. The contact portion includes a first zigzag structure, a second zigzag structure, a third zigzag structure, and a fourth zigzag structure. A first end of the first zigzag structure, a first end of the fourth zigzag structure, and a first end of the reference zigzag structure are directly connected with the first common line. A first end of the second zigzag structure, a first end of the third zigzag structure, and a second end of the reference zigzag structure are directly connected with the second common line. The reference zigzag structure is disposed between the first zigzag structure and the second zigzag structure. A line width of the reference zigzag structure is equal to a line width of the first zigzag structure.
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公开(公告)号：US11887895B2
公开(公告)日：2024-01-30
申请号：US17343756
申请日：2021-06-10
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/02 , H01L29/10 , H01L29/66 , H01L29/78 , H10B10/00 , H01L21/265 , H01L21/02 , H01L27/092 , H01L29/06
CPC分类号： H01L21/823412 , H01L21/0262 , H01L21/26513 , H01L21/823481 , H01L21/823493 , H01L21/823807 , H01L21/823892 , H01L21/84 , H01L27/0207 , H01L27/0921 , H01L29/0653 , H01L29/105 , H01L29/1079 , H01L29/1083 , H01L29/66545 , H01L29/66568 , H01L29/66628 , H01L29/7834 , H01L29/7838 , H10B10/00 , H10B10/12
摘要： Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
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公开(公告)号：US20220283600A1
公开(公告)日：2022-09-08
申请号：US17191719
申请日：2021-03-04
发明人： Yoshihiko Matsuo
摘要： A voltage regulator includes an operational amplifier, a first transistor, a second transistor, a capacitor and a current sink circuit. The operational amplifier outputs a control voltage according to an amplified differential voltage between a first input terminal and a second input terminal of the operational amplifier. The first transistor includes a control terminal receiving the control voltage, a first terminal coupled to a supply terminal, a second terminal providing an output voltage, and a bulk terminal. The second transistor includes a second terminal coupled to the bulk terminal of the first transistor, and a bulk terminal coupled to the supply terminal. The capacitor includes a first terminal coupled to the bulk terminal of the first transistor, and a second terminal receiving the output voltage. The current sink circuit generates a feedback voltage according to the output voltage and output the feedback voltage to the operational amplifier.
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公开(公告)号：US20220063873A1
公开(公告)日：2022-03-03
申请号：US17010818
申请日：2020-09-02
发明人： Takihiko Satonaka
摘要： A bottle cap is disclosed. The bottle cap includes a cap body having a cover plate and a cylinder part integral with the cover plate. A stopper member protrudes from an inner surface of the cover plate. The stopper member includes a sealing part supported by a support structure integral with the cover plate. An annular guiding plate protrudes from a sidewall surface of the cylinder part and is inclined toward the stopper member to engage with the sealing part.
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公开(公告)号：US11177359B2
公开(公告)日：2021-11-16
申请号：US16807614
申请日：2020-03-03
发明人： Toru Anezaki , Fumitaka Ohno
IPC分类号： H01L29/165 , H01L27/092 , H01L29/423 , H01L29/66 , H01L29/06
摘要： A semiconductor device includes a semiconductor substrate, a gate electrode disposed over the semiconductor substrate and extending in a first direction, a dummy gate electrode disposed over the semiconductor substrate away from the gate electrode and extending in the first direction, a first semiconductor area of a first conductive type disposed in a surface layer portion of the semiconductor substrate between the gate electrode and the dummy gate electrode, and a conductor electrically connecting the first semiconductor area with the dummy gate electrode.
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公开(公告)号：US20210313231A1
公开(公告)日：2021-10-07
申请号：US17343756
申请日：2021-06-10
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/02 , H01L27/11 , H01L29/10 , H01L29/66 , H01L29/78 , H01L21/265 , H01L21/02 , H01L27/092 , H01L29/06
摘要： Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
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公开(公告)号：US10818594B2
公开(公告)日：2020-10-27
申请号：US16409225
申请日：2019-05-10
发明人： Taiji Ema , Makoto Yasuda , Kazuhiro Mizutani
IPC分类号： H01L23/528 , H01L27/11573 , H01L29/423 , H01L29/792 , H01L21/8234 , H01L27/088
摘要： There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
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公开(公告)号：US10741699B2
公开(公告)日：2020-08-11
申请号：US16273534
申请日：2019-02-12
发明人： Taiji Ema , Makoto Yasuda
IPC分类号： H01L29/792 , H01L27/06
摘要： A semiconductor device includes a gate insulator layer above a semiconductor substrate, a gate electrode above the gate insulating layer, a sidewall insulator layer on sidewalls of the gate electrode and above the substrate, source and drain regions within the substrate on both sides of the gate electrode, a first region within the substrate below a part of the sidewall insulator layer closer to the source region and having an impurity concentration lower than the source region, a second region provided within the substrate below a part of the sidewall insulator layer closer to the drain region and having an impurity concentration lower than the drain region, a channel region provided within the substrate between the first and second regions, and a third region within the substrate below the channel region and including impurities of a different type and having an impurity concentration higher than the channel region.
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公开(公告)号：US20240014259A1
公开(公告)日：2024-01-11
申请号：US18370883
申请日：2023-09-21
发明人： Fumitaka Ohno , Makoto Yasuda
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/66
CPC分类号： H01L29/0638 , H01L29/1033 , H01L29/4236 , H01L29/66621
摘要： A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and drain regions being a first conductivity type respectively disposed at two sides of the gate structure. The doped region being a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and drain region, the doped region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and a dopant concentration of the channel region is less than a dopant concentration of the doped region.
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公开(公告)号：US20230187445A1
公开(公告)日：2023-06-15
申请号：US17989676
申请日：2022-11-17
发明人： Narumi Ohkawa
IPC分类号： H01L27/092 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/775 , H01L21/822 , H01L21/8238 , H01L29/66
CPC分类号： H01L27/0922 , H01L21/8221 , H01L21/823807 , H01L21/823814 , H01L29/0673 , H01L29/775 , H01L29/0847 , H01L29/42392 , H01L29/66439 , H01L29/66545
摘要： A semiconductor device having a transistor with fin structure includes a channel layer that is disposed over a substrate and is connected to the substrate via a semiconductor layer, a source layer that is disposed on a first side surface of the channel layer over the substrate and is separated from the substrate via a first insulating layer, a drain layer that is disposed on a second side surface of the channel layer opposite to the first side surface over the substrate and is separated from the substrate via a second insulating layer, and a gate electrode including a first portion disposed over the channel layer and a second portion which is disposed between the substrate and the channel layer and whose third side surface or fourth side surface faces the semiconductor layer.
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