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公开(公告)号：US12022203B2
公开(公告)日：2024-06-25
申请号：US18011777
申请日：2021-06-22
摘要： The present disclosure relates to a processing arrangement for converting digital image data. Conventional approaches suffer from speed or non-ideal compressing schemes. These drawbacks are overcome by the processing arrangement for determining a digital output value from a digital input value based on a linear function and a square root function. The processing arrangement includes a first calculation block configured to determine a first output value of the linear function, a second calculation block configured to determine a second output value of the square root function. A selector is configured to select, based on a comparison between the digital input value and a threshold value, whether the digital output value is determined by the first calculation block or by the second calculation block.
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公开(公告)号：US11653115B2
公开(公告)日：2023-05-16
申请号：US17429709
申请日：2020-01-23
发明人： Adi Xhakoni , Ali Jaderi , Guy Meynants
IPC分类号： H04N5/369 , H04N5/3745
CPC分类号： H04N5/36963 , H04N5/3698 , H04N5/37455
摘要： An image sensor system has a pixel array with a plurality of pixels, each of the pixels comprising a photodiode, a pixel buffer and a transfer gate coupled between the photodiode and an input of the pixel buffer. A voltage supply block is configured to generate a pixel supply voltage from an input voltage based on a first reference voltage and to provide the pixel supply voltage to the pixel array. A calibration processing block is configured to determine an average pixel signal based on an average of individual pixel signals at outputs of the pixels of the pixel array and to determine a correction value based on the average pixel signal and a reference pixel signal. A correction processing block is configured to determine the first reference voltage based on a combination of a second reference voltage and the correction value.
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公开(公告)号：US20240333294A1
公开(公告)日：2024-10-03
申请号：US18682119
申请日：2022-08-25
发明人： Adi XHAKONI
IPC分类号： H03M1/12
CPC分类号： H03M1/122
摘要： An ADC circuit includes a comparator with a first input for receiving an analog signal and with a second input for receiving a ramp signal, a first output of the comparator, a second output of the comparator, a first counter connected to the first output, a second counter connected to the second output, a first clock connected to the first counter, and a second clock connected to the second counter. The first clock provides a first clock signal to the first counter, the second clock provides a second clock signal to the second counter, the first counter is configured to count with the frequency of the first clock signal, the second counter is configured to count with the frequency of the second clock signal. The frequency of the first clock signal is lower than the frequency of the second clock signal.
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公开(公告)号：US12096140B2
公开(公告)日：2024-09-17
申请号：US17818962
申请日：2022-08-10
发明人： Denver Lloyd , Adi Xhakoni , Scott Johnson
IPC分类号： H04N25/59 , H01L27/146 , H04N25/531 , H04N25/583 , H04N25/585 , H04N25/62 , H04N25/75 , H04N25/778
CPC分类号： H04N25/59 , H01L27/14612 , H01L27/14643 , H04N25/531 , H04N25/583 , H04N25/585 , H04N25/62 , H04N25/75 , H04N25/778
摘要： In an embodiment a pixel arrangement includes a photodetector configured to accumulate charge carriers by converting electromagnetic radiation, a transfer transistor electrically coupled to the photodetector, a diffusion node electrically coupled to the transfer transistor, a reset transistor electrically coupled to the diffusion node and to a pixel supply voltage and a sample-and-hold stage including at least a first capacitor and a second capacitor, an input of the sample-and-hold stage being electrically coupled to the diffusion node via an amplifier, wherein the transfer transistor is configured to be pulsed to different voltage levels for transferring parts of the accumulated charge carriers to the diffusion node, wherein at least the second capacitor is configured to store a low conversion gain signal representing a first part of the accumulated charge carriers, and wherein the first capacitor is configured to store a high conversion gain signal representing a remaining part of the accumulated charge carriers.
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公开(公告)号：US20240244347A1
公开(公告)日：2024-07-18
申请号：US18563888
申请日：2022-05-31
发明人： Jason INMAN , Kevin FRONCZAK
IPC分类号： H04N25/625 , H04N25/75
CPC分类号： H04N25/625 , H04N25/75
摘要： An imaging pixel to mitigate cross-talk effects comprises a voltage supply node to receive a supply voltage, and an output node to provide a pixel output signal. The imaging pixel further comprises a photosensitive element, and a source follower transistor having a control node coupled to the photosensitive element. The source follower transistor is interposed between the voltage supply node and the output node. The imaging pixel comprises a clamping circuit being interposed between the voltage supply node and the output node.
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公开(公告)号：US20240107196A1
公开(公告)日：2024-03-28
申请号：US18257114
申请日：2021-12-14
发明人： Dong-Long LIN
IPC分类号： H04N25/771 , H04N25/707 , H04N25/708
CPC分类号： H04N25/771 , H04N25/707 , H04N25/708
摘要： An optical sensor includes an array of pixels, wherein each pixel includes a photodiode configured to receive an optical signal and a floating node coupled to the photodiode. At least one sensing path is capacitively coupled to the floating node of at least one of the pixels. An evaluation unit is coupled to the at least one sensing path to generate an electrical signal dependent on the optical signal received by the photodiode.
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公开(公告)号：US20230361136A1
公开(公告)日：2023-11-09
申请号：US18246398
申请日：2021-09-15
发明人： Dong-Long LIN , Adi XHAKONI
IPC分类号： H01L27/146
CPC分类号： H01L27/14603 , H01L27/14649 , H01L27/1463 , H01L27/14645 , H01L27/14621
摘要： A pixel structure includes a substrate body having a light entrance surface, a plurality of first photodiodes formed in the substrate body at a first depth with respect to the light entrance surface, and a second photodiode formed in the substrate body at a second depth with respect to the light entrance surface. The first depth corresponds to a photon absorption length in a material of the substrate body at a first wavelength range, and the second depth corresponds to a photon absorption length in the material of the substrate body at a second wavelength range that is different from the first wavelength range.
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公开(公告)号：US11770640B2
公开(公告)日：2023-09-26
申请号：US17440327
申请日：2020-02-05
发明人： Wesley Cotteleer
IPC分类号： H04N25/772 , H03M1/00 , H03M1/06 , H04N25/75 , H04N25/71 , H04N25/771
CPC分类号： H04N25/772 , H03M1/002 , H03M1/0624 , H04N25/745 , H04N25/75 , H04N25/771
摘要： An analog-to-digital converter for an image sensor comprises a counter circuit to generate a respective counter bit in response to a counter state of the counter circuit, and a storage circuit for storing a respective storage state in response the respective counter bit. The converter further comprises a comparator circuit for generating a level of a comparison signal, and a synchronization circuit to generate a write control signal for controlling the storing of the respective storage state in the respective storage cell. The counter circuit is configured to change the counter state, when a first edge of a cycle of the clock signal is applied to the counter circuit, and to generate the write control signal, when a second edge of the cycle of the clock signal being subsequent to the first edge of the cycle of the clock signal is applied to the synchronization circuit.
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公开(公告)号：US20230054015A1
公开(公告)日：2023-02-23
申请号：US17792285
申请日：2020-12-08
发明人： Adi XHAKONI
IPC分类号： G01J1/44 , H04N5/33 , H04N5/3745 , H04N5/369
摘要： A pixel cell comprises a plurality of pixels, each pixel comprising a photodiode, a readout circuit comprising a first readout component and a second readout component, wherein a first group of the pixels is configured to detect electromagnetic radiation in a first wavelength range, a second group of the pixels is configured to detect electromagnetic radiation in a second wavelength range, the first readout component is connected with the first group of pixels, the second readout component is connected with the second group of pixels, the first wavelength range is different from the second wavelength range, and the second readout component comprises a plurality of storage capacitors, wherein each pixel of the second group of pixels is assigned to at least one of the storage capacitors, or the second readout component comprises a memory element. Furthermore, a method for operating a pixel cell is provided.
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公开(公告)号：US20220408040A1
公开(公告)日：2022-12-22
申请号：US17352776
申请日：2021-06-21
发明人： Jason INMAN , Kevin FRONCZAK
摘要： An imaging pixel (2) to mitigate cross-talk effects comprises a voltage supply node (VN) to receive a supply voltage (VDD), and an output node (ON) to provide a pixel output signal. The imaging pixel (2) further comprises a photosensitive element (10), and a source follower transistor (31) having a control node coupled to the photosensitive element (10). The source follower transistor (31) is interposed between the voltage supply node (VN) and the output node (ON). The imaging pixel (2) comprises a clamping circuit (20) being interposed between the voltage supply node (VN) and the output node (ON).
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