公开(公告)号：US09236967B1

公开(公告)日：2016-01-12

申请号：US13799086

申请日：2013-03-13

申请人： Integrated Device Technology, Inc.

发明人： Frederic Mustiere ,  Russell Smiley ,  Felix Duong ,  Alain Trottier ,  Durrey Farooqui ,  Peng Xiao

IPC分类号： H04J3/06

CPC分类号： H04J3/0661 ,  H04J3/0667

摘要： Methods of packet-based synchronization in non-stationary network environments can include accumulating timestamps transmitted in packets between master and slave devices that are separated from each other by a packet network. Operations are also performed to determine whether first timestamps accumulated in a first direction across the packet network demonstrate that a first packet delay variation (PDV) sequence observed from the first timestamps is stationary. Thereafter, estimates of at least one of frequency skew and phase offset between the master and slave clocks are acquired using a first algorithm, from the first timestamps accumulated in the first direction. These operations of determining further include determining whether second timestamps accumulated in a second direction demonstrate that a second packet delay variation (PDV) sequence observed from the second timestamps is stationary.

摘要翻译： 在非固定网络环境中基于分组的同步的方法可以包括在通过分组网络彼此分离的主设备和从设备之间的分组中累积传输的时间戳。 还执行操作以确定跨分组网络在第一方向上累积的第一时间戳是否显示从第一时间戳观察到的第一分组延迟变化（PDV）序列是静止的。 此后，从第一方向累积的第一时间戳，使用第一算法获取主时钟与从时钟之间的频率偏移和相位偏移中的至少一个的估计。 进一步确定的这些操作还包括确定在第二方向上累积的第二时间戳是否表明从第二时间戳观察到的第二分组延迟变化（PDV）序列是静止的。

公开(公告)号：US09065459B1

公开(公告)日：2015-06-23

申请号：US13829202

申请日：2013-03-14

申请人： Integrated Device Technology, Inc.

发明人： Brian Buell

IPC分类号： H03L7/087 ,  H03L7/197 ,  H03L7/22

CPC分类号： H03L7/087 ,  H03L7/1974 ,  H03L7/1976 ,  H03L7/235

摘要： An apparatus includes a phase locked loop (PLL) circuit configured to generate a PLL output signal from an oscillator signal and a control circuit configured to generate a measure of a difference between the PLL output signal and an input clock signal at a control output thereof. The apparatus further includes a dynamic range shifter circuit coupling the control output of the control circuit to a control input (e.g., a feedback divider control input) of the PLL circuit and configured to shift a dynamic range of the control output of the control circuit with respect to a dynamic range of the control input of the PLL circuit. The apparatus may be implemented with an oscillator, such as a MEMs oscillator, in a single chip.

摘要翻译： 一种装置包括：锁相环（PLL）电路，被配置为从振荡器信号产生PLL输出信号;以及控制电路，被配置为在其控制输出处产生PLL输出信号与输入时钟信号之间的差值的量度。 该装置还包括动态范围移动器电路，其将控制电路的控制输出耦合到PLL电路的控制输入（例如，反馈分配器控制输入），并被配置为将控制电路的控制输出的动态范围与 相对于PLL电路的控制输入的动态范围。 该装置可以用单个芯片中的诸如MEM振荡器的振荡器来实现。

公开(公告)号：US08826057B1

公开(公告)日：2014-09-02

申请号：US13538643

申请日：2012-06-29

申请人： Bruce Lorenz Chin ,  David Stuart Gibson

发明人： Bruce Lorenz Chin ,  David Stuart Gibson

IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00

CPC分类号： G11C7/1084 ,  G06F13/4054 ,  G11C7/109 ,  G11C7/1093 ,  H04L7/0045

摘要： A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of inputs electrically coupled to outputs of a corresponding plurality of delay elements in the data pipeline. The latency selection circuit is configured to pass a data pipeline signal from an output of a selected one of the plurality of delay elements in response to a latency control signal. A synchronization circuit is provided, which is electrically coupled to an output of the latency selection circuit. This synchronization circuit, which includes first and second unequal timing paths therein, is responsive to a clock that synchronizes capture of the data pipeline signal selected by the latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured data pipeline signal as active.

摘要翻译： 多时域同步器包括其中包含多个串联连接的延迟元件的数据流水线。 提供了一种等待时间选择电路，其具有电耦合到数据流水线中对应的多个延迟元件的输出的多个输入。 等待时间选择电路被配置为响应于等待时间控制信号而从多个延迟元件中选择的一个的输出传递数据流水线信号。 提供同步电路，其电连接到等待时间选择电路的输出端。 该同步电路包括其中的第一和第二不相等的定时路径，其响应于等待时间选择电路选择的数据流水线信号的捕获与选择第一和第二不等时序路径之一的目的地代码的时钟 被捕获的数据流水线信号遍历为活动状态。

公开(公告)号：US08742854B1

公开(公告)日：2014-06-03

申请号：US13186332

申请日：2011-07-19

申请人： Seungbae Lee ,  Harmeet Bhugra ,  Ashwin Samarao

发明人： Seungbae Lee ,  Harmeet Bhugra ,  Ashwin Samarao

IPC分类号： H03B21/01 ,  H03B5/30

CPC分类号： H03H9/02448 ,  H03H9/02259 ,  H03H9/2405 ,  H03H9/2463 ,  H03H2009/0244 ,  H03H2009/02496 ,  H03H2009/2415

摘要： A periodic signal generator is configured to generate high frequency signals characterized by relatively low temperature coefficients of frequency (TCF). A microelectromechanical resonator, such as concave bulk acoustic resonator (CBAR) supporting capacitive and piezoelectric transduction, may be geometrically engineered as a signal generator that produces two periodic signals having unequal resonant frequencies with unequal temperature coefficients. Circuitry is also provided for combining the two periodic signals using a mixer to thereby yield a high frequency low-TCF periodic difference signal at an output of the periodic signal generator.

摘要翻译： 周期性信号发生器被配置为产生由频率相对较低的温度系数（TCF）表征的高频信号。 支持电容和压电转换的诸如凹体积声共振器（CBAR）的微电子机械谐振器可以被几何地设计为信号发生器，其产生具有不等于具有不等温度系数的不等谐振频率的两个周期信号。 还提供电路用于使用混频器组合两个周期信号，从而在周期信号发生器的输出处产生高频低TCF周期性差分信号。

公开(公告)号：US08559587B1

公开(公告)日：2013-10-15

申请号：US13425761

申请日：2012-03-21

申请人： Brian Buell ,  Benedykt Mika ,  Chen-Wei Huang

发明人： Brian Buell ,  Benedykt Mika ,  Chen-Wei Huang

IPC分类号： H03K21/00

CPC分类号： H03K23/662 ,  H03K23/68

摘要： Fractional-N divider circuits include a multi-modulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multi-modulus divider. A divider modulation circuit is provided, which is configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by the multi-modulus divider. The divider modulation circuit includes a segmented accumulator, which is configured to generate a plurality of segments of a count value having at least one period of latency therebetween.

摘要翻译： 分数N分频器电路包括多模式分频器，其被配置为对在其第一输入处接收的第一参考信号执行至少/ N和/ N + 1分频。 响应于在其第二输入处接收的溢出信号执行该除法，其中N是大于1的整数。 相位校正电路被配置为响应于由多模式分频器产生的分频器输出信号而产生第二参考信号。 提供了一种分频器调制电路，其被配置为响应于指定由多模式分频器使用的多个分频模块的代码产生溢出信号。 分频器调制电路包括分段累加器，其被配置为生成具有至少一个等待时间段的计数值的多个段。

公开(公告)号：US07825777B1

公开(公告)日：2010-11-02

申请号：US11393489

申请日：2006-03-30

申请人： Tingjun Wen ,  David Walter Carr ,  Tadeusz Kwasniewski

发明人： Tingjun Wen ,  David Walter Carr ,  Tadeusz Kwasniewski

IPC分类号： G05B1/00 ,  H03K19/20 ,  H03K19/094 ,  G06F7/00

CPC分类号： G06F7/026

摘要： An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1, . . . , 0]) and a second n-bit operand (e.g., B[n−1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal Co (or its complement), where: C o = ( … ⁡ ( ( C i ⁡ ( A 0 + B 0 _ ) + A 0 ⁢ B 0 _ ) ⁢ ( A 1 + B 1 _ ) + A 1 ⁢ B 1 _ ) ⁢ … ⁡ ( A n - 2 + B n - 2 _ ) + A n - 2 ⁢ B n - 2 _ ) ⁢ ( A n - 1 + B n - 1 _ ) + A n - 1 ⁢ B n - 1 _ , “n” is a positive integer greater than one and Ci is a control input signal that specifies an interpretation to be given to the control output signal Co.

摘要翻译： 提供集成电路比较器，其确定施加到其上的操作数之间的非严格不等式。 每个比较器包括至少一个n位比较器单元。 该比较器单元被配置为确定第一n位操作数（例如，A [n-1，...，0]）和第二n位操作数之间的非严格不等式（例如，B [n-1 ，...，0]）。 比较器单元通过计算控制输出信号Co（或其补码）来确定非严格不等式，其中：C o =（...⁡（（C 0⁡（A 0 + B 0 _）+ A 0 B 0 _ ）（A 1 + B 1 _）+ A 1 B 1 _）...⁡（A n-2 + B n-2 _）+ A n-2 B n-2 _）（A n- 1 + B n - 1 _）+ A n - 1 B n - 1 _，“n”是大于1的正整数，Ci是指定给予控制输出信号Co的解释的控制输入信号 。

公开(公告)号：US08943242B1

公开(公告)日：2015-01-27

申请号：US13436324

申请日：2012-03-30

申请人： David Stuart Gibson ,  Bruce Lorenz Chin

发明人： David Stuart Gibson ,  Bruce Lorenz Chin

IPC分类号： G06F5/00

CPC分类号： G06F5/065

摘要： A timing controller includes a pipelined delay chain configured to process commands and control signals associated with the commands between a first device and a plurality of second devices having different timing requirements. The pipelined delay chain includes a cascaded arrangement of a primary delay chain, at least one secondary delay chain and a plurality of control signal sequence generators responsive to signals generated by the at least one secondary delay chain. The primary delay chain may include a plurality of serially-linked registers configured to support a pipelining of the commands and a stack configured to support operations to push and pop the control signals associated with the commands to and from the stack.

摘要翻译： 定时控制器包括流水线延迟链，其被配置为处理与第一设备和具有不同时序要求的多个第二设备之间的命令相关联的命令和控制信号。 流水线延迟链包括响应于由至少一个次级延迟链产生的信号的主延迟链，至少一个次级延迟链和多个控制信号序列发生器的级联布置。 主延迟链可以包括被配置为支持命令的流水线的多个串行连接的寄存器，以及被配置为支持操作以将与命令相关联的控制信号推送到堆栈并从堆栈弹出的堆栈。

公开(公告)号：US08680931B1

公开(公告)日：2014-03-25

申请号：US13435817

申请日：2012-03-30

申请人： Wanling Pan

发明人： Wanling Pan

IPC分类号： H03B5/32 ,  H03B21/00 ,  H01L41/083 ,  H01L41/18 ,  H03H9/205 ,  H03H9/25

CPC分类号： H03H9/02448 ,  H03H2009/2415

摘要： A periodic signal generator is configured to generate high frequency signals characterized by relatively low temperature coefficients of frequency (TCF). This generator may include an oscillator containing a pair of equivalent MEMs resonators therein, which are configured to support bulk acoustic wave and surface wave modes of operation at different resonance frequencies. Each resonator includes a stack of layers including a semiconductor resonator body (e.g., Si-body), a piezoelectric layer (e.g., AIN layer) on the resonator body and interdigitated drive and sense electrodes on the piezoelectric layer. The oscillator is configured to support the generation of first and second periodic signals having unequal first and second frequencies (f1, f2) from first and second resonators within the pair. These first and second periodic signals are characterized by respective first and second temperature coefficients of frequency (TCf1, TCf2), which may differ by at least about 10 ppm/° C.

摘要翻译： 周期性信号发生器被配置为产生由频率相对较低的温度系数（TCF）表征的高频信号。 该发生器可以包括在其中包含一对等效MEM谐振器的振荡器，其被配置为支持在不同共振频率下的体声波和表面波模式的操作。 每个谐振器包括一叠层，包括半导体谐振器体（例如Si体），谐振器体上的压电层（例如，AIN层）和交错驱动以及压电层上的感测电极。 振荡器被配置为支持从该对内的第一和第二谐振器产生具有不等的第一和第二频率（f1，f2）的第一和第二周期信号。 这些第一和第二周期信号的特征在于相应的第一和第二频率温度系数（TCf1，TCf2），其可以相差至少约10ppm /℃。

公开(公告)号：US08638178B1

公开(公告)日：2014-01-28

申请号：US13407484

申请日：2012-02-28

申请人： Ye Wang

发明人： Ye Wang

IPC分类号： H03B5/18

CPC分类号： H03H3/0075 ,  H03H2009/241

摘要： Methods of testing packaged thin-film piezoelectric-on-semiconductor (TPoS) microelectromechanical resonators having hermetic seals include measuring a quality factor (Q) of resonance of the packaged resonator at at least two unequal temperatures to determine whether a ΔQ/ΔT is significantly different (e.g, by at least 50%) over a temperature range (ΔT) spanning a smallest and largest of the at least two temperatures. These measurements are performed for a packaged resonator having a QAIR

摘要翻译： 测试封装的具有气密密封的薄膜压电半导体（TPoS）微机电谐振器的方法包括在至少两个不等温度下测量封装谐振器的谐振的质量因子（Q），以确定DeltaQ / DeltaT是否显着不同 （例如，至少50％）在跨越至少两个温度中最小和最大的温度范围（DeltaT）。 对于具有QAIR

公开(公告)号：US08501515B1

公开(公告)日：2013-08-06

申请号：US13035148

申请日：2011-02-25

申请人： Wanling Pan

发明人： Wanling Pan

IPC分类号： H01L41/00

CPC分类号： H03H3/02 ,  H03H9/02228 ,  H03H9/172 ,  H03H9/564 ,  H03H2003/0407 ,  H03H2003/0478

摘要： Methods of forming electro-micromechanical resonators provide passive temperature compensation of semiconductor device layers used therein. A first substrate is provided that includes a first electrically insulating temperature compensation layer on a first semiconductor device layer. A step is performed to bond the first electrically insulating temperature compensation layer to a second substrate containing the second electrically insulating temperature compensation layer therein, to thereby form a relatively thick temperature compensation layer. A piezoelectric layer is formed on the first electrically insulating temperature compensation layer and at least a first electrode is formed on the piezoelectric layer.

摘要翻译： 形成电微机械谐振器的方法为其中使用的半导体器件层提供无源温度补偿。 提供了第一衬底，其包括在第一半导体器件层上的第一电绝缘温度补偿层。 执行步骤，将第一电绝缘温度补偿层与包含第二电绝缘温度补偿层的第二基板结合，从而形成相对较厚的温度补偿层。 在第一电绝缘温度补偿层上形成压电层，并且在压电层上形成至少第一电极。