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公开(公告)号:US12131915B2
公开(公告)日:2024-10-29
申请号:US18325905
申请日:2023-05-30
发明人: Jheng-Hong Jiang , Chia-Wei Liu , Shing-Huang Wu
IPC分类号: H01L21/321 , C22C21/12 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号: H01L21/3212 , C22C21/12 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/53219 , H01L23/53223
摘要: A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.
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公开(公告)号:US12124270B2
公开(公告)日:2024-10-22
申请号:US17265455
申请日:2018-09-15
发明人: Jun Liu , Zixiang Wang , Weizhang Luo , Mei Wu Fang , Tiequan Luo
CPC分类号: G05D1/0253 , G06T7/20 , G06T7/70
摘要: Various embodiments include methods for improving navigation by a processor of a robotic device equipped with an image sensor and an optical flow sensor. The robotic device may be configured to capture or receive two image frames from the image sensor, generate a homograph computation based on the image frames, receive optical flow sensor data from an optical flow sensor, and determine a scale estimation value based on the homograph computation and the optical flow sensor data. The robotic device may determine the robotic device pose (or the pose of the image sensor) based on the scale estimation value.
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公开(公告)号:US12121615B2
公开(公告)日:2024-10-22
申请号:US17267541
申请日:2020-01-08
申请人: ATLANGRAM
发明人: Olivier Meyer , Amokrane Reghal
CPC分类号: A61K9/5123 , A61K9/5153 , A61K9/5161 , A61K38/12 , A61P19/00 , A61P31/04
摘要: The present invention relates to a pharmaceutical composition stabilized in a gelled state at at least a temperature varying from 15° C. to 40° C., comprising at least one aqueous phase gelled with at least one hydrophilic polymeric gelling agent, lipid nanocapsules comprising a liquid or semi-liquid lipid core at room temperature enveloped in a lipid envelope which is solid at room temperature, said gelled aqueous phase and nanocapsules containing at least one antibiotic, identical or different, the antibiotic in said aqueous phase being present there in the form of a solute.
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公开(公告)号:US12119482B2
公开(公告)日:2024-10-15
申请号:US17322181
申请日:2021-05-17
申请人: NANOGRAF CORPORATION
发明人: Cary Michael Hayner , Aaron Yost , Kathryn Hicks , Seonbaek Ha , Pitawat Mahawattanangul , Joshua J. Lau
IPC分类号: H01M4/133 , H01M4/134 , H01M4/136 , H01M4/36 , H01M4/38 , H01M4/48 , H01M4/58 , H01M4/583 , H01M4/587 , H01M4/62 , H01M10/0525 , H01M4/02
CPC分类号: H01M4/366 , H01M4/133 , H01M4/134 , H01M4/136 , H01M4/382 , H01M4/386 , H01M4/483 , H01M4/5825 , H01M4/587 , H01M4/622 , H01M10/0525 , H01M2004/027
摘要: Active material composite particles, an electrode including the composite particles, a lithium ion secondary battery including the electrode, and method of forming the same, in which the composite particles each include a core particle including an alkali metal or an alkali earth metal silicate, and a coating disposed on the surface of the core particle. The coating includes turbostratic carbon having a Raman spectrum having: a D band having a peak intensity (ID) at wave number between 1330 cm−1 and 1360 cm−1; a G band having a peak intensity (IG) at wave number between 1580 cm−1 and 1600 cm−1; and a 2D band having a peak intensity (I2D) at wave number between 2650 cm−1 and 2750 cm−1, wherein a ratio of ID/IG ranges from greater than zero to about 1.1, and a ratio of I2D/IG ranges from about 0.4 to about 2.
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公开(公告)号:US12113099B2
公开(公告)日:2024-10-08
申请号:US18359023
申请日:2023-07-26
发明人: Fu-Chiang Kuo
IPC分类号: H01G4/35 , H01L23/532 , H01L49/02 , H01L21/285 , H01L29/94
CPC分类号: H01L28/60 , H01G4/35 , H01L21/2855 , H01L23/5329 , H01L28/91 , H01L29/945
摘要: A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.
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公开(公告)号:US12112321B2
公开(公告)日:2024-10-08
申请号:US16699071
申请日:2019-11-28
发明人: Prakash Tiwari , Shvetank Kumar Singh , Rajesh Yadav , Naga Chandan Babu Gudivada , Vidyasagar Gopireddy , Manish Sharma , Utkarsh Mehta
IPC分类号: G06Q20/32 , G06F9/451 , G06F16/23 , G06F21/53 , G06F21/57 , G06Q20/10 , G06Q20/36 , G06Q20/38 , G06Q20/40 , G06Q40/06 , H04L29/06 , H04W12/06 , H04W12/08 , G06F21/31 , G06F21/32 , G06F21/45 , G06Q20/34 , G06Q40/02 , H04W4/14 , H04W12/062 , H04W12/72 , H04W60/00
CPC分类号: G06Q20/3823 , G06F9/451 , G06F21/53 , G06F21/57
摘要: Various embodiments include methods and devices for implementing a secure user interface. The method may include generating a secure user interface display in a secure execution environment, generating a non-secure display in a normal execution environment, combining the secure user interface and the non-secure display into a combined display, and presenting the combined display via a display device.
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公开(公告)号:US12101936B2
公开(公告)日:2024-09-24
申请号:US17523487
申请日:2021-11-10
发明人: Tatsuya Hinoue , Yusuke Mukae , Ryousuke Itou , Masanori Tsutsumi , Akio Nishida , Ramy Nashed Bassely Said
IPC分类号: H01L27/11582 , H10B41/27 , H10B43/27
摘要: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.
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公开(公告)号:US12100730B2
公开(公告)日:2024-09-24
申请号:US18501396
申请日:2023-11-03
发明人: Po-Chia Lai , Stefan Rusu , Chun-Yen Lee
IPC分类号: H01L23/522 , H01L21/768 , H01L27/08 , H01L49/02
CPC分类号: H01L28/60 , H01L21/76838 , H01L23/5223 , H01L23/5226 , H01L27/0805
摘要: Integrated circuit (IC) devices include a metal-insulator-metal (MIM) capacitor having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate. A plurality of dielectric layers may separate each of the electrode plates of the MIM capacitor from adjacent plates of the MIM capacitor. Each of the intermediate electrode plates may have a thickness that is greater than a thickness of the top electrode plate and the bottom electrode plate. By providing multiple intermediate electrode plates between the top and bottom electrode plates of the MIM capacitor, and allocating the greatest plate thicknesses to the intermediate plates, the capacitance density may be increased in a given area of the IC device, which may provide increased performance for the IC device.
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公开(公告)号:US12099397B2
公开(公告)日:2024-09-24
申请号:US18069537
申请日:2022-12-21
发明人: Prashanth Kumar Kakkireni , Matthew Severson , Ravi Jenkal , Gordon Lee , Kevin Bradley Citterelle , Ronald Alton , Anish Muttreja
IPC分类号: G06F1/32 , G06F1/3296
CPC分类号: G06F1/3296
摘要: Various embodiments include power management system methods including receiving, at a processor(s), a notification signal triggering the processor(s) to implement power usage mitigation at the processor(s), determining, by the processor(s), a mitigation amount of power rail power by which to mitigate current usage at a power rail based on a use case for the power rail, and implementing power usage mitigation at the processor(s) by the processor(s) sufficient to mitigate power usage at the power rail by the mitigation amount of power rail power. Power usage mitigation may include reducing processor(s) current usage: by a predefined amount; proportional to the amount a power rail current exceeds a power rail current threshold; by the amount of current exceeding a processor current threshold; or by a smallest amount between the amount a power rail current exceeds a power rail current threshold and the processor(s) current exceeds a processor current threshold.
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公开(公告)号:US12098590B2
公开(公告)日:2024-09-24
申请号:US17839023
申请日:2022-06-13
申请人: Joshua Glover
发明人: Joshua Glover
CPC分类号: E06B5/10 , E06B9/0692 , F41H5/24
摘要: Various embodiments include bullet-resistant multilayered curtain that can be quickly deployed to secure an entranceway from attackers and deter them from entering. A bullet-resistant multilayered curtain may be contained above an entranceway in a casing and supported by a quick release pin when in the stored configuration. The bullet-resistant curtain includes multiple horizontal bars that are distributed along the length of the bullet-resistant curtain. Firmly fixed on the perimeter of the entranceway are horizontal bar retainer clamps for locking the horizontal bars into place when the bullet-resistant curtain is in its deployed state. A vibration sensor control switch may be fixed on the perimeter of the entranceway and configured to activate vibration sensors fixed on the bullet-resistant curtain to detect vibrations and send notifications to remote authorities.
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