公开(公告)号：US4855800A

公开(公告)日：1989-08-08

申请号：US96176

申请日：1987-09-11

申请人： Agerico L. Esquivel ,  Robert Groover, III ,  Howard L. Tigelaar

发明人： Agerico L. Esquivel ,  Robert Groover, III ,  Howard L. Tigelaar

IPC分类号： H01L21/28 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76216 ,  H01L21/76224 ,  H01L27/115

摘要： Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

摘要翻译： 公开了具有高速编程能力的浮动栅极存储器阵列。 扩散掩埋位线（14）在半导体中间隔开形成，在其间形成传导通道。 介电填充沟槽（24）形成在位线（14）之间。 绝缘浮栅导体（18）和绝缘控制栅极导体（23）形成在晶片之上并被图案化以在电介质填充的沟槽（24）上延伸。 控制栅极（23）和浮动栅极（18）之间增强的耦合效率提高了存储器单元的可编程性。

公开(公告)号：US4892840A

公开(公告)日：1990-01-09

申请号：US336265

申请日：1989-04-11

申请人： Agerico L. Esquivel ,  Robert Groover, III ,  Howard L. Tigelaar

发明人： Agerico L. Esquivel ,  Robert Groover, III ,  Howard L. Tigelaar

IPC分类号： H01L21/28 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76216 ,  H01L21/76224 ,  H01L27/115

摘要： Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

摘要翻译： 公开了具有高速编程能力的浮动栅极存储器阵列。 扩散掩埋位线（14）在半导体中间隔开形成，在其间形成传导通道。 介电填充沟槽（24）形成在位线（14）之间。 绝缘浮栅导体（18）和绝缘控制栅极导体（23）形成在晶片之上并被图案化以在电介质填充的沟槽（24）上延伸。 控制栅极（23）和浮动栅极（18）之间增强的耦合效率提高了存储器单元的可编程性。

公开(公告)号：US4931411A

公开(公告)日：1990-06-05

申请号：US287808

申请日：1988-12-20

申请人： Howard L. Tigelaar ,  Roger A. Haken ,  Thomas C. Holloway ,  Robert Groover, III

发明人： Howard L. Tigelaar ,  Roger A. Haken ,  Thomas C. Holloway ,  Robert Groover, III

IPC分类号： H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11

CPC分类号： H01L27/11526 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3211 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823835 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11543 ,  Y10S148/113 ,  Y10S148/147

摘要： Disclosed is an integrated circuit process which includes forming two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices. The TiN gates in the second set of transistors and the TiN interconnect are formed by providing a thin film insulator pattern, depositing a titanium layer overall, heating the titanium in a nitrogen bearing atmosphere, and subsequently etching the titanium nitride obtained.

摘要翻译： 公开了一种集成电路工艺，其包括形成两种类型的有源器件：第一组IGFET具有硅化物栅极，第二组具有TiN栅极。 相同的TiN薄膜层也提供局部互连。 可选地，TiN栅极器件可用于高电压器件和用于逻辑器件的硅化物栅极器件。 第二组晶体管和TiN互连中的TiN栅极通过提供薄膜绝缘体图案，整体沉积钛层，在含氮气氛中加热钛，随后蚀刻所获得的氮化钛而形成。

公开(公告)号：US4814854A

公开(公告)日：1989-03-21

申请号：US938699

申请日：1986-12-05

申请人： Howard L. Tigelaar ,  Roger A. Haken ,  Thomas C. Holloway ,  Robert Groover, III

发明人： Howard L. Tigelaar ,  Roger A. Haken ,  Thomas C. Holloway ,  Robert Groover, III

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L27/11526 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11543 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S257/915

摘要： A new integrated circuit structure which includes two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices.

摘要翻译： 一种新的集成电路结构，其包括两种类型的有源器件：第一组IGFET具有硅化物栅极，第二组具有TiN栅极。 相同的TiN薄膜层也提供局部互连。 可选地，TiN栅极器件可用于高电压器件和用于逻辑器件的硅化物栅极器件。

公开(公告)号：US5241303A

公开(公告)日：1993-08-31

申请号：US814338

申请日：1991-12-26

申请人： David S. Register ,  J. Michael O'Dell ,  Robert Groover, III

发明人： David S. Register ,  J. Michael O'Dell ,  Robert Groover, III

IPC分类号： G06F1/16 ,  G06F3/023

CPC分类号： G06F1/1637 ,  G06F1/1615 ,  G06F1/162 ,  G06F1/1654 ,  G06F1/1656 ,  G06F1/1669 ,  G06F3/0231

摘要： A computer system which is reconfigurable to provide separate ergonomically advantageous positions for keyboard input and for stylus input. A primary system chassis contains a bay in its underside where a detachable keyboard can be stored. For one-hand stylus input, the keyboard is left in its bay while the display is mounted flat on top of the system chassis. For keyboard input, the keyboard is mounted on the system chassis, and the display is supported at an angle which makes it easily visible to a user typing on the keyboard.

摘要翻译： 一种计算机系统，其可重新配置以为键盘输入和触控笔输入提供单独的符合人体工程学的有利位置。 主系统底盘在其底部包含一个可以存储可拆卸键盘的托架。 对于单手触控笔输入，键盘留在其托架中，而显示屏平放在系统机箱的顶部。 对于键盘输入，键盘安装在系统机箱上，并且显示器以一定角度被支持，这使得用户在键盘上打字时可以方便地看到。

公开(公告)号：US5010386A

公开(公告)日：1991-04-23

申请号：US457030

申请日：1989-12-26

申请人： Robert Groover, III

发明人： Robert Groover, III

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092

CPC分类号： H01L27/092

摘要： A complementary semiconductor structure comprises a substrate of a first conductivity type upon which a first channel layer of a second conductivity type is formed. The first source/drain layer of the first conductivity type is formed on the surface of the first channel layer and an insulating layer is formed on the surface of the first source/drain layer. A second source/drain layer of the second conductivity type is formed on the surface of the insulating layer and a second channel layer of said first conductivity is formed on the surface of the second source/drain layer. A third source/drain layer of the second conductivity type is formed on the surface of the second channel layer. Gate circuitry is vertically disposed on an edge perpendicular to the plane and adjacent to the first and second channel layers and insulated therefrom.

摘要翻译： 互补半导体结构包括第一导电类型的衬底，在其上形成第二导电类型的第一沟道层。 第一导电类型的第一源极/漏极层形成在第一沟道层的表面上，并且在第一源极/漏极层的表面上形成绝缘层。 第二导电类型的第二源极/漏极层形成在绝缘层的表面上，并且在第二源极/漏极层的表面上形成所述第一导电性的第二沟道层。 第二导电类型的第三源极/漏极层形成在第二沟道层的表面上。 栅极电路垂直设置在垂直于该平面并且与第一和第二沟道层相邻并且与其绝缘的边缘上。

公开(公告)号：US4804636A

公开(公告)日：1989-02-14

申请号：US837443

申请日：1986-03-07

申请人： Robert Groover, III ,  Roger A. Haken ,  Thomas C. Holloway

发明人： Robert Groover, III ,  Roger A. Haken ,  Thomas C. Holloway

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/11 ,  H01L21/283

CPC分类号： H01L27/11526 ,  H01L21/32053 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11543 ,  Y10S148/02 ,  Y10S148/147

摘要： Disclosed is a process for making VLSI integrated circuits and a local interconnect system, wherein first poly, second poly and moat are all interconnected in any desired pattern by a TiN local interconnect. No masks are required beyond those which would be required for the two poly levels and local interconnect capability anyway.

摘要翻译： 公开了一种用于制造VLSI集成电路和局部互连系统的方法，其中第一聚，第二聚和护环全部以TiN局部互连以任何所需的图案互连。 除了两个多层次和本地互连能力所需的掩模之外，不需要掩模。