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    Vertical memory devices and methods of manufacturing the same
    1.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权
    垂直存储器件及其制造方法

    公开(公告)号：US09324730B2

    公开(公告)日：2016-04-26

    申请号：US14601496

    申请日：2015-01-21

    Applicant: Phil-Ouk Nam ,  Dong-Chul Yoo ,  Bi-O Kim ,  Jae-Young Ahn ,  Byong-Hyun Jang ,  Ki-Hyun Hwang

    Inventor： Phil-Ouk Nam ,  Dong-Chul Yoo ,  Bi-O Kim ,  Jae-Young Ahn ,  Byong-Hyun Jang ,  Ki-Hyun Hwang

    IPC: H01L29/792 ,  H01L27/115 ,  H01L27/02

    CPC classification number: H01L27/11582 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157

    Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

    Abstract translation: 一种垂直存储器件，包括：包括第一区域和第二区域的衬底; 所述第一区域中的多个通道，所述多个通道在基本上垂直于所述基板的顶表面的第一方向上延伸; 每个通道的侧壁上的电荷存储结构，其基本上平行于所述基板的顶表面; 所述第一区域中的多个栅极电极，所述多个栅电极设置在所述电荷存储结构的侧壁上，并且在所述第一方向上彼此间隔开; 以及在所述第二区域中的多个支撑件，所述多个支撑件在基本上垂直于所述第一方向和所述第二方向的第三方向上彼此间隔开，所述多个支撑件接触至少一个栅电极的侧壁。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130032878A1

    公开(公告)日：2013-02-07

    申请号：US13560022

    申请日：2012-07-27

    Applicant: Bi-O Kim ,  Byong-Ju Kim ,  Jung-Geun Jee ,  Jin-Gyun Kim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    Inventor： Bi-O Kim ,  Byong-Ju Kim ,  Jung-Geun Jee ,  Jin-Gyun Kim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    IPC: H01L29/78 ,  H01L29/02

    CPC classification number: H01L27/1157 ,  H01L27/11582 ,  H01L29/105

    Abstract: According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.

    Abstract translation: 根据示例性实施例，半导体器件包括堆叠在衬底上的水平图案。 水平图案通过水平图案定义开口。 第一个核心模式是在开幕。 第一个核心模式是第一个核心模式的开放。 第一活动模式在第一芯图案和水平图案之间。 包含第一元件的第二活动图案位于第二芯图案和水平图案之间。 第二活性图案含有比第二芯图案中的第一元素的浓度高的浓度的第一元素。

    Semiconductor memory device and method of manufacturing the same
    3.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09530899B2

    公开(公告)日：2016-12-27

    申请号：US14474942

    申请日：2014-09-02

    Applicant: Bi O Kim ,  Jin-Tae Noh ,  Su-Jin Shin ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    Inventor： Bi O Kim ,  Jin-Tae Noh ,  Su-Jin Shin ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    IPC: H01L29/792 ,  H01L27/115 ,  G11C16/04 ,  H01L21/28 ,  H01L29/66

    CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833

    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括交替层叠在基板上的绝缘层和栅极电极，垂直通过绝缘层和栅电极的垂直沟道，以及设置在垂直线之间的阈值电压控制绝缘层，隧道绝缘层和电荷存储层 沟道和栅电极，其中所述阈值电压控制绝缘层设置在所述电荷存储层和所述垂直沟道之间，并且包括被配置为抑制在所述垂直沟道中形成反型层的材料。

    Semiconductor device including a first core pattern under a second core pattern
    4.
    发明授权
    Semiconductor device including a first core pattern under a second core pattern 有权
    半导体器件包括在第二芯图案下的第一芯图案

    公开(公告)号：US09129857B2

    公开(公告)日：2015-09-08

    申请号：US13560022

    申请日：2012-07-27

    Applicant: Bi-O Kim ,  Byong-Ju Kim ,  Jung-Geun Jee ,  Jin-Gyun Kim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    Inventor： Bi-O Kim ,  Byong-Ju Kim ,  Jung-Geun Jee ,  Jin-Gyun Kim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    IPC: H01L29/792 ,  H01L27/115 ,  H01L21/336

    CPC classification number: H01L27/1157 ,  H01L27/11582 ,  H01L29/105

    Abstract: According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.

    Abstract translation: 根据示例性实施例，半导体器件包括堆叠在衬底上的水平图案。 水平图案通过水平图案定义开口。 第一个核心模式是在开幕。 第一个核心模式是第一个核心模式的开放。 第一活动模式在第一芯图案和水平图案之间。 包含第一元件的第二活动图案位于第二芯图案和水平图案之间。 第二活性图案含有比第二芯图案中的第一元素的浓度高的浓度的第一元素。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20150129954A1

    公开(公告)日：2015-05-14

    申请号：US14474942

    申请日：2014-09-02

    Applicant: Bi O. Kim ,  Jin-Tae Noh ,  Su-Jin Shin ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    Inventor： Bi O. Kim ,  Jin-Tae Noh ,  Su-Jin Shin ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    IPC: H01L29/792

    CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833

    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括交替层叠在基板上的绝缘层和栅极电极，垂直通过绝缘层和栅电极的垂直沟道，以及设置在垂直线之间的阈值电压控制绝缘层，隧道绝缘层和电荷存储层 沟道和栅电极，其中所述阈值电压控制绝缘层设置在所述电荷存储层和所述垂直沟道之间，并且包括被配置为抑制在所述垂直沟道中形成反型层的材料。

    Vertical Memory Devices and Methods of Manufacturing the Same
    6.
    发明申请
    Vertical Memory Devices and Methods of Manufacturing the Same 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20140024189A1

    公开(公告)日：2014-01-23

    申请号：US13943911

    申请日：2013-07-17

    Applicant: Bi-O Kim ,  Toshiro Nakanishi ,  Jin-Tae Noh ,  Chang-Woo Sun ,  Seung-Hyun Lim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    Inventor： Bi-O Kim ,  Toshiro Nakanishi ,  Jin-Tae Noh ,  Chang-Woo Sun ,  Seung-Hyun Lim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    IPC: H01L29/66

    CPC classification number: H01L29/66666 ,  H01L21/8239 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.

    Abstract translation: 提供制造垂直存储器件的方法包括在衬底上形成多个交替绝缘层和牺牲层; 图案化和蚀刻所述多个绝缘层和牺牲层以限定暴露所述衬底的表面的至少一部分的开口; 在开口的侧壁上形成电荷捕获图案和隧道绝缘图案; 在开口的侧壁上的隧道绝缘层上形成沟道层，沟道层包括N型杂质掺杂多晶硅; 在开口中的沟道层上形成掩埋绝缘图案; 以及在沟道层的一个侧壁的电荷捕获图案上形成阻挡电介质层和控制栅极。

    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    8.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20150206900A1

    公开(公告)日：2015-07-23

    申请号：US14601496

    申请日：2015-01-21

    Applicant: Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

    Inventor： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157

    Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

    Abstract translation: 一种垂直存储器件，包括：包括第一区域和第二区域的衬底; 所述第一区域中的多个通道，所述多个通道在基本上垂直于所述基板的顶表面的第一方向上延伸; 每个通道的侧壁上的电荷存储结构，其基本上平行于所述基板的顶表面; 所述第一区域中的多个栅极电极，所述多个栅电极设置在所述电荷存储结构的侧壁上，并且在所述第一方向上彼此间隔开; 以及在所述第二区域中的多个支撑件，所述多个支撑件在基本上垂直于所述第一方向和所述第二方向的第三方向上彼此间隔开，所述多个支撑件接触至少一个栅电极的侧壁。

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