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公开(公告)号：US20120133535A1
公开(公告)日：2012-05-31
申请号：US13382735
申请日：2010-07-08
Applicant: Bob Verbruggen
Inventor： Bob Verbruggen
CPC classification number: H03M1/002 , H03M1/1023 , H03M1/1215 , H03M1/1235 , H03M1/164 , H03M1/361 , H03M1/445
Abstract: The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed.
Abstract translation: 本发明涉及一种用于将模拟输入信号转换成数字信号的流水线模数转换器ADC，该数字信号包括：具有可调阈值的多个比较装置，用于比较输入信号; 所述给定阈值中的至少两个是不同的，以及多个放大电路，其中所述多个比较装置被配置为形成分级树结构，所述分级树结构具有多个层级，其中至少一个所述 层级与所述多个放大电路中的至少一个放大电路相关联，所述至少一个放大电路在下一层级产生至少一个比较装置的输入，其中所述多个层级包括用于设置所述多个放大电路的装置， 根据先前层次级别的输出，可调整的阈值，从而消除前一级别级别的非线性失真。
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Patent Agency Ranking
公开(公告)号：US08618973B2
公开(公告)日：2013-12-31
申请号：US13382735
申请日：2010-07-08
Applicant: Bob Verbruggen
Inventor： Bob Verbruggen
CPC classification number: H03M1/002 , H03M1/1023 , H03M1/1215 , H03M1/1235 , H03M1/164 , H03M1/361 , H03M1/445
Abstract: The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed.
Abstract translation: 本发明涉及一种用于将模拟输入信号转换成数字信号的流水线模数转换器ADC，该数字信号包括：具有可调阈值的多个比较装置，用于比较输入信号; 所述给定阈值中的至少两个是不同的，以及多个放大电路，其中所述多个比较装置被配置为形成分级树结构，所述分级树结构具有多个层级，其中至少一个所述 层级与所述多个放大电路中的至少一个放大电路相关联，所述至少一个放大电路在下一层级产生至少一个比较装置的输入，其中所述多个层级包括用于设置所述多个放大电路的装置， 根据先前层次级别的输出，可调整的阈值，从而消除前一级别级别的非线性失真。
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3.发明授权公开(公告)号：US08384578B2
公开(公告)日：2013-02-26
申请号：US13192056
申请日：2011-07-27
Applicant: Bob Verbruggen , Jan Craninckx
Inventor： Bob Verbruggen , Jan Craninckx
Abstract: An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described. The A/D converter circuit includes: a first converter stage configured for receiving the analog input signal and for generating a first set of conversion bits, a first completion signal and a residual analog output signal representing the difference between the analog input signal and a signal represented by said first set of conversion bits, a second converter stage comprising a clock generation circuit arranged for receiving the first completion signal and for generating a clock signal, a plurality of comparators each being configured for receiving the residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by the clock signal and for outputting a plurality of comparator decisions, a digital processing stage configured for receiving the plurality of comparator decisions and for generating a second set of conversion bits, means for generating the digital representation of the analog input signal by combining the first and second set of conversion bits.
Abstract translation: 描述了用于接收模拟输入信号并输出所述模拟输入信号的数字表示的模拟（A / D）转换器电路。 A / D转换器电路包括：第一转换器级，被配置为接收模拟输入信号并产生第一组转换位，第一完成信号和表示模拟输入信号与信号之间的差的残留模拟输出信号 由所述第一组转换位表示的第二转换器级，包括布置成用于接收第一完成信号并用于产生时钟信号的时钟产生电路，多个比较器被配置为用于接收残留模拟输出信号和公共参考 电压，所述多个比较器被布置成被时钟信号激活并用于输出多个比较器判定;数字处理级，被配置用于接收多个比较器判决并用于产生第二组转换位，用于产生数字 通过组合第一个a来表示模拟输入信号 第二组转换位。
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公开(公告)号：US08199043B2
公开(公告)日：2012-06-12
申请号：US12863149
申请日：2009-01-22
Applicant: Geert Van der Plas , Bob Verbruggen
Inventor： Geert Van der Plas , Bob Verbruggen
IPC: H03M1/38
CPC classification number: H03M1/125 , H03M1/002 , H03M1/1235 , H03M1/361 , H03M1/42
Abstract: An analog-to-digital converter that uses a comparator based asynchronous binary search is described. The architecture includes a self-clocked (asynchronous) hierarchical binary tree of comparators, each arranged for being provided with a predetermined threshold. The input signal is applied in parallel to all comparators as is the case with flash converters, but the clock is applied to (at least) one comparator only, for example to the first or root comparator. The at least one comparator is further arranged for controlling at least one other comparator of the plurality of comparators.
Abstract translation: 描述了使用基于比较器的异步二进制搜索的模数转换器。 该架构包括比较器的自定时（异步）分层二进制树，每个被布置成具有预定阈值。 输入信号与闪存转换器的情况并行地应用于所有比较器，但是时钟仅施加到（至少）一个比较器，例如到第一个或根比较器。 所述至少一个比较器还被布置用于控制所述多个比较器中的至少一个其它比较器。
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公开(公告)号：US20100328120A1
公开(公告)日：2010-12-30
申请号：US12863149
申请日：2009-01-22
Applicant: Geert Van der Plas , Bob Verbruggen
Inventor： Geert Van der Plas , Bob Verbruggen
CPC classification number: H03M1/125 , H03M1/002 , H03M1/1235 , H03M1/361 , H03M1/42
Abstract: The present invention is related to an analog-to-digital converter circuit (1) wherein a comparator based asynchronous binary search is used. The architecture comprises a self-clocked (asynchronous) hierarchical binary tree of comparators, each arranged for being provided with a predetermined threshold. The input signal is applied in parallel to all comparators as is the case with flash converters, but the clock is applied to (at least) one comparator (2) only, preferably to the first or root comparator. The at least one comparator (2) is further arranged for controlling at least one other comparator (3) of the plurality of comparators (2, 3, 4).
Abstract translation: 本发明涉及一种使用基于比较器的异步二进制搜索的模数转换器电路（1）。 该架构包括比较器的自定时（异步）分层二进制树，每个布置为提供预定阈值。 输入信号与闪存转换器的情况一样并行地施加到所有比较器，但是时钟仅施加到（至少）一个比较器（2），优选地应用于第一或根比较器。 所述至少一个比较器（2）还被布置用于控制所述多个比较器（2,3,4）中的至少一个其它比较器（3）。
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6.发明申请公开(公告)号：US20130015988A1
公开(公告)日：2013-01-17
申请号：US13192056
申请日：2011-07-27
Applicant: Bob Verbruggen , Jan Craninckx
Inventor： Bob Verbruggen , Jan Craninckx
Abstract: An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described. The A/D converter circuit includes: a first converter stage configured for receiving the analog input signal and for generating a first set of conversion bits, a first completion signal and a residual analog output signal representing the difference between the analog input signal and a signal represented by said first set of conversion bits, a second converter stage comprising a clock generation circuit arranged for receiving the first completion signal and for generating a clock signal, a plurality of comparators each being configured for receiving the residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by the clock signal and for outputting a plurality of comparator decisions, a digital processing stage configured for receiving the plurality of comparator decisions and for generating a second set of conversion bits, means for generating the digital representation of the analog input signal by combining the first and second set of conversion bits.
Abstract translation: 描述了用于接收模拟输入信号并输出所述模拟输入信号的数字表示的模拟（A / D）转换器电路。 A / D转换器电路包括：第一转换器级，被配置为接收模拟输入信号并产生第一组转换位，第一完成信号和表示模拟输入信号与信号之间的差的残留模拟输出信号 由所述第一组转换位表示的第二转换器级，包括布置成用于接收第一完成信号并用于产生时钟信号的时钟产生电路，多个比较器被配置为用于接收残留模拟输出信号和公共参考 电压，所述多个比较器被布置成被时钟信号激活并用于输出多个比较器判定;数字处理级，被配置用于接收多个比较器判决并用于产生第二组转换位，用于产生数字 通过组合第一个a来表示模拟输入信号 第二组转换位。
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