公开(公告)号：US20080315307A1

公开(公告)日：2008-12-25

申请号：US12204339

申请日：2008-09-04

Applicant: Cheng Yu FANG ,  Sheng Yuan Yang ,  Wei Jung Chen

Inventor： Cheng Yu FANG ,  Sheng Yuan Yang ,  Wei Jung Chen

IPC: H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/66659 ,  H01L29/7835

Abstract: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current.

Abstract translation: 高电压装置包括半导体衬底和栅极。 半导体衬底包括具有第一导电类型的第一掺杂区域，具有第二导电类型的第二掺杂区域，具有第二导电类型的第三掺杂区域，围绕第三掺杂区域并具有第二导电类型的第四掺杂区域， 以及围绕所述第三掺杂区域并具有所述第二导电类型的第五掺杂区域。 栅极设置在两个间隔物之间​​以将第二掺杂区域与第三掺杂区域分离，以便控制第二掺杂区域和第三掺杂区域的导通。 在高电压器件中，第五掺杂区域包围第三掺杂区域，以便加强第三掺杂区域的覆盖，并改善第三掺杂区域底部的离子浓度均匀性，以减少漏电流。

公开(公告)号：US07075107B2

公开(公告)日：2006-07-11

申请号：US10841035

申请日：2004-05-06

Applicant: Wei-Jung Chen ,  Yung-Ching Chang ,  Jaw-Shin Huang ,  Cheng-Yu Fang ,  Chien-Peng Yu

Inventor： Wei-Jung Chen ,  Yung-Ching Chang ,  Jaw-Shin Huang ,  Cheng-Yu Fang ,  Chien-Peng Yu

IPC: H01L23/58

CPC classification number: H01L22/32

Abstract: A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line, and a conductive arrangement including at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.

Abstract translation: 半导体晶片包括晶片体，多个模拟IC晶体管间隔地并排成型地形成在晶片体上，以在每个两个晶片之间形成边界，形成划线，其中每一个晶片具有形成在其中的至少一个内部电路 端子焊盘，以及导电装置，其至少包括形成在晶片体上的导电元件，以使端子焊盘与芯片的内部电路电连接，使得当芯片从晶片切断时 主体沿着划线，将端子焊盘从模具切断，以将内部电路保持在模具中。

公开(公告)号：US20100052056A1

公开(公告)日：2010-03-04

申请号：US12273530

申请日：2008-11-18

Applicant: Yen-Wei Liao ,  Sheng-Yuan Yang ,  Cheng-Yu Fang

Inventor： Yen-Wei Liao ,  Sheng-Yuan Yang ,  Cheng-Yu Fang

IPC: H01L29/78

CPC classification number: H01L29/86 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection device includes a substrate with a doped well of a first conductive type, a first and a second doping region of the first conductive type and a third and a fourth doping region of a second conductive type respectively disposed in the doped well, a first gate disposed on the substrate and between the first and the second doping region, and a second gate disposed on the substrate and between the second and the third doping region to determine the distance between the second and the third doping region in order to precisely adjust the breakdown voltage of the ESD protection device of the present invention.

Abstract translation: ESD保护装置包括具有第一导电类型的掺杂阱，第一导电类型的第一和第二掺杂区以及分别设置在掺杂阱中的第二导电类型的第三和第四掺杂区的衬底， 第一栅极，其设置在衬底上并且在第一和第二掺杂区域之间，以及第二栅极，其设置在衬底上并且在第二和第三掺杂区域之间，以确定第二和第三掺杂区域之间的距离，以便精确地调整 本发明的ESD保护器件的击穿电压。

公开(公告)号：US20060113602A1

公开(公告)日：2006-06-01

申请号：US10999722

申请日：2004-11-29

Applicant: Cheng-Yu Fang ,  Wei-Jung Chen ,  Sheng-Ti Lee ,  Chien-Peng Yu ,  Yi-Cheng Wang

Inventor： Cheng-Yu Fang ,  Wei-Jung Chen ,  Sheng-Ti Lee ,  Chien-Peng Yu ,  Yi-Cheng Wang

IPC: H01L29/94

CPC classification number: H01L27/0266 ,  H01L29/78

Abstract: A MOS circuit arrangement includes a silicon substrate, a semiconductor device, a field oxide layer, and a poly-protective layer. The silicon substrate has a conductive doping incorporated therein, wherein the semiconductor device is electrically connected with the silicon substrate. The field oxide layer is formed on the silicon substrate at a position spaced apart from the terminal of the semiconductor device to form an active region between the field oxide layer and the semiconductor device. The poly-protective layer deposited on the active region to communicate the field oxide layer with the terminal of the semiconductor device, wherein the poly-protective layer provides a junction breakdown path between the semiconductor device and the silicon substrate to increase a junction breakdown voltage of the semiconductor device.

Abstract translation: MOS电路装置包括硅衬底，半导体器件，场氧化物层和多保护层。 硅衬底具有掺入其中的导电掺杂，其中半导体器件与硅衬底电连接。 场氧化物层形成在硅衬底上与半导体器件的端子间隔开的位置处，以在场氧化物层和半导体器件之间形成有源区。 沉积在有源区上的多晶硅保护层将场氧化物层与半导体器件的端子连通，其中多晶硅保护层在半导体器件和硅衬底之间提供结击穿通路径，以增加晶体管的击穿电压 半导体器件。

公开(公告)号：US20050282361A1

公开(公告)日：2005-12-22

申请号：US11167967

申请日：2005-06-27

Applicant: Wei-Jung Chen ,  Yung-Ching Chang ,  Jaw-Shin Huang ,  Cheng-Yu Fang ,  Chien-Peng Yu

Inventor： Wei-Jung Chen ,  Yung-Ching Chang ,  Jaw-Shin Huang ,  Cheng-Yu Fang ,  Chien-Peng Yu

IPC: H01L21/301 ,  H01L21/44 ,  H01L23/544

CPC classification number: H01L22/32

Abstract: A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line, and a conductive arrangement including at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.

Abstract translation: 半导体晶片包括晶片体，多个模拟IC晶体管间隔地并排成型地形成在晶片体上，以在每个两个晶片之间形成边界，形成划线，其中每一个晶片具有形成在其中的至少一个内部电路 端子焊盘，以及导电装置，其至少包括形成在晶片体上的导电元件，以使端子焊盘与芯片的内部电路电连接，使得当芯片从晶片切断时 主体沿着划线，将端子焊盘从模具切断，以将内部电路保持在模具中。

公开(公告)号：US20050248000A1

公开(公告)日：2005-11-10

申请号：US10841035

申请日：2004-05-06

Applicant: Wei-Jung Chen ,  Yung-Ching Chang ,  Jaw-Shin Huang ,  Cheng-Yu Fang ,  Chien-Peng Yu

Inventor： Wei-Jung Chen ,  Yung-Ching Chang ,  Jaw-Shin Huang ,  Cheng-Yu Fang ,  Chien-Peng Yu

IPC: H01L21/301 ,  H01L21/44 ,  H01L23/544

CPC classification number: H01L22/32

Abstract: A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line, and a conductive arrangement including at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.

公开(公告)号：US6117798A

公开(公告)日：2000-09-12

申请号：US215654

申请日：1998-12-16

Applicant: Cheng-Yu Fang ,  Chih-Chiang Liu

Inventor： Cheng-Yu Fang ,  Chih-Chiang Liu

IPC: H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/316 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31058

Abstract: A method of spin-on-glass planarization. A spin-on-glass layer is formed on a substrate. An accuflo layer with a better fluidity than the spin-on-glass material is formed on the spin-on-glass layer. The accuflo layer and the spin-on-glass layer are etched back by two etching steps with different etching rate. The accuflo layer after being etched is stripped. A dielectric layer is formed.

Abstract translation: 旋涂玻璃平面化方法。 在基板上形成旋涂玻璃层。 在旋涂玻璃层上形成具有比旋涂玻璃材料更好的流动性的凝集层。 通过不同蚀刻速率的两个蚀刻步骤对accuflo层和旋涂玻璃层进行回蚀。 蚀刻后的腐蚀层剥离。 形成介电层。

公开(公告)号：US20080054309A1

公开(公告)日：2008-03-06

申请号：US11621517

申请日：2007-01-09

Applicant: Cheng Yu Fang ,  Sheng Yuan Yang ,  Wei Jung Chen

Inventor： Cheng Yu Fang ,  Sheng Yuan Yang ,  Wei Jung Chen

IPC: H01L29/76

CPC classification number: H01L29/0847 ,  H01L29/66659 ,  H01L29/7835

Abstract: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current.

Abstract translation: 高电压装置包括半导体衬底和栅极。 半导体衬底包括具有第一导电类型的第一掺杂区域，具有第二导电类型的第二掺杂区域，具有第二导电类型的第三掺杂区域，围绕第三掺杂区域并具有第二导电类型的第四掺杂区域， 以及围绕所述第三掺杂区域并具有所述第二导电类型的第五掺杂区域。 栅极设置在两个间隔物之间​​以将第二掺杂区域与第三掺杂区域分离，以便控制第二掺杂区域和第三掺杂区域的导通。 在高电压器件中，第五掺杂区域包围第三掺杂区域，以便加强第三掺杂区域的覆盖，并改善第三掺杂区域底部的离子浓度均匀性，以减少漏电流。

公开(公告)号：US20050268186A1

公开(公告)日：2005-12-01

申请号：US10841915

申请日：2004-05-06

Applicant: Wei-Jung Chen ,  Yung-Ching Chang ,  Jaw-Shin Huang ,  Cheng-Yu Fang ,  Chien-Peng Yu

Inventor： Wei-Jung Chen ,  Yung-Ching Chang ,  Jaw-Shin Huang ,  Cheng-Yu Fang ,  Chien-Peng Yu

IPC: G01R31/28 ,  G11C29/00

CPC classification number: G01R31/2831

Abstract: A semiconductor wafer includes a wafer body, a plurality of dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two the dies, wherein at least one of the dies is formed as a tested die having a terminal pad for measuring a voltage of the tested die via a measuring tool, and a test circuit having an output end and an input end electrically extended from an internal circuit of the tested die. An output impedance of the test circuit is relatively smaller than an impedance of the measuring tool, such that the voltage of the tested die adapted for being precisely measured when testing terminals of the measuring tool are electrically pointed at the tested die and the output end of the test circuit respectively.

Abstract translation: 半导体晶片包括晶片体，多个晶片间隔地并排成型地形成在晶片本体上，以限定划线作为在两个模具之间形成的边界，其中至少一个模具形成为具有 端子焊盘，用于经由测量工具测量被测试的裸片的电压;以及测试电路，其具有从被测试的裸片的内部电路电扩展的输出端和输入端。 测试电路的输出阻抗相对小于测量工具的阻抗，使得当测量工具的测试端子的电极指向被测试模具时，适合于精确测量的被测试模具的电压， 测试电路。

公开(公告)号：US20100090284A1

公开(公告)日：2010-04-15

申请号：US12323475

申请日：2008-11-26

Applicant: Yen-Wei Liao ,  Sheng-Yuan Yang ,  Cheng-Yu Fang

Inventor： Yen-Wei Liao ,  Sheng-Yuan Yang ,  Cheng-Yu Fang

IPC: H01L29/78

CPC classification number: H01L27/0266 ,  H01L29/42368 ,  H01L29/78

Abstract: A metal-oxide-semiconductor device includes a substrate, a gate on the substrate, a source in the substrate and adjacent to one side of the gate, a drain in the substrate and adjacent to another side of the gate, a gate channel in the substrate and under the gate, and a gate insulator between the source and the drain and the gate and the gate channel, wherein the gate insulator has a substantially uneven thickness for use in electrostatic discharge (ESD) protection.

Abstract translation: 金属氧化物半导体器件包括衬底，衬底上的栅极，衬底中的源极和栅极的一侧相邻，衬底中的漏极和与栅极的另一侧相邻的栅极沟道 衬底和栅极之下，以及源极和漏极以及栅极和栅极通道之间的栅极绝缘体，其中栅极绝缘体具有用于静电放电（ESD）保护的基本上不均匀的厚度。