公开(公告)号：US08629066B2

公开(公告)日：2014-01-14

申请号：US13562101

申请日：2012-07-30

Applicant: Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L21/336

CPC classification number: H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L2221/68372 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.

Abstract translation: 集成电路结构包括半导体衬底; 贯穿半导体衬底的贯通半导体通孔（TSV）开口; 和TSV开口的TSV衬管。 TSV衬套包括在TSV开口的侧壁上的侧壁部分和TSV开口底部的底部。 TSV衬管的底部部分的底部高度大于TSV衬套的侧壁部分的中间厚度。

公开(公告)号：US08405192B2

公开(公告)日：2013-03-26

申请号：US12893374

申请日：2010-09-29

Applicant: Hsin-Yen Huang ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao

Inventor： Hsin-Yen Huang ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/58

CPC classification number: H01L21/02203 ,  C08G77/50 ,  C09D183/14 ,  C23C16/30 ,  C23C18/122 ,  C23C18/1254 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH3 groups. The dielectric material including the additive may be used as an inter-layer dielectric (ILD) layer of a semiconductor device. The dielectric material including the additive may be formed using a CVD or sol-gel process. One example of the additive is bis(triethoxysilyl)ethene.

Abstract translation: 本公开提供了包括低介电常数材料和添加剂的介电材料。 添加剂包括具有Si-X-Si桥的化合物，其中X是1至8之间的碳原子数。该添加剂可以包括末端Si-CH 3基团。 包括添加剂的电介质材料可以用作半导体器件的层间电介质（ILD）层。 可以使用CVD或溶胶 - 凝胶法形成包括添加剂的电介质材料。 添加剂的一个实例是双（三乙氧基甲硅烷基）乙烯。

公开(公告)号：US20110006428A1

公开(公告)日：2011-01-13

申请号：US12617900

申请日：2009-11-13

Applicant: Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L23/48

CPC classification number: H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L2221/68372 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.

Abstract translation: 集成电路结构包括半导体衬底; 贯穿半导体衬底的贯通半导体通孔（TSV）开口; 和TSV开口的TSV衬管。 TSV衬套包括在TSV开口的侧壁上的侧壁部分和TSV开口底部的底部。 TSV衬管的底部部分的底部高度大于TSV衬套的侧壁部分的中间厚度。

公开(公告)号：US20100123224A1

公开(公告)日：2010-05-20

申请号：US12271617

申请日：2008-11-14

Applicant: Bo-Jiun Lin ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao ,  Chen-Hua Yu

Inventor： Bo-Jiun Lin ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao ,  Chen-Hua Yu

IPC: H01L23/58 ,  H01L21/312

CPC classification number: H01L21/3121 ,  C23C18/1212 ,  C23C18/122 ,  C23C18/1254 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02304

Abstract: A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.

Abstract translation: 公开了一种提供改进的机械强度的半导体器件和制造方法。 半导体器件包括半导体衬底; 设置在半导体衬底上的粘附层; 以及设置在所述半导体衬底上的多孔低k膜，其中所述多孔低k膜包含致孔剂和包含至少一个Si-O-Si键合基团和至少一个桥连有机官能团的复合键合结构。

公开(公告)号：US08836127B2

公开(公告)日：2014-09-16

申请号：US12621569

申请日：2009-11-19

Applicant: Ching-Yu Lo ,  Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Ching-Yu Lo ,  Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L23/53295 ,  H01L23/5329 ,  H01L24/02 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00

Abstract: An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion.

Abstract translation: 集成电路装置具有双镶嵌结构，其包括下通孔部分和上线部分。 下通孔部分形成在聚酰亚胺层中，并且上部分部分形成在由USG或聚酰亚胺形成的金属间电介质（IMD）层中。 在IMD层上形成钝化层，并且形成覆盖钝化层的接合焊盘以电连接上部线部分。

公开(公告)号：US20120074535A1

公开(公告)日：2012-03-29

申请号：US12893374

申请日：2010-09-29

Applicant: Hsin-Yen Huang ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao

Inventor： Hsin-Yen Huang ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L29/06 ,  H01L21/31 ,  C09D183/06

CPC classification number: H01L21/02203 ,  C08G77/50 ,  C09D183/14 ,  C23C16/30 ,  C23C18/122 ,  C23C18/1254 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH3 groups. The dielectric material including the additive may be used as an inter-layer dielectric (ILD) layer of a semiconductor device. The dielectric material including the additive may be formed using a CVD or sol-gel process. One example of the additive is bis(triethoxysilyl)ethene.

Abstract translation: 本公开提供了包括低介电常数材料和添加剂的介电材料。 添加剂包括具有Si-X-Si桥的化合物，其中X是1至8之间的碳原子数。该添加剂可以包括末端Si-CH 3基团。 包括添加剂的电介质材料可以用作半导体器件的层间电介质（ILD）层。 可以使用CVD或溶胶 - 凝胶法形成包括添加剂的电介质材料。 添加剂的一个实例是双（三乙氧基甲硅烷基）乙烯。

公开(公告)号：US20110115088A1

公开(公告)日：2011-05-19

申请号：US12621569

申请日：2009-11-19

Applicant: Ching-Yu Lo ,  Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Ching-Yu Lo ,  Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L23/48

CPC classification number: H01L23/53295 ,  H01L23/5329 ,  H01L24/02 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00

Abstract: An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion.

Abstract translation: 集成电路装置具有双镶嵌结构，其包括下通孔部分和上线部分。 下通孔部分形成在聚酰亚胺层中，并且上部分部分形成在由USG或聚酰亚胺形成的金属间电介质（IMD）层中。 在IMD层上形成钝化层，并且形成覆盖钝化层的接合焊盘以电连接上部线部分。

公开(公告)号：US20080074065A1

公开(公告)日：2008-03-27

申请号：US11636492

申请日：2006-12-11

Applicant: Ching-Yu Lo

Inventor： Ching-Yu Lo

IPC: H02P7/00

CPC classification number: F04D25/166

Abstract: A complex signal processing system for multiple fans is used to control the rotation of a first fan and a second fan. The speed signals of the first fan and the second fan are processed through an XOR operation to obtain a complex speed signal. In response to the complex speed signal, the speed and the operational status of the first fan and the second fan can be evaluated.

Abstract translation: 用于多个风扇的复杂信号处理系统用于控制第一风扇和第二风扇的旋转。 通过异或运算来处理第一风扇和第二风扇的速度信号以获得复合速度信号。 响应于复合速度信号，可以评估第一风扇和第二风扇的速度和操作状态。

公开(公告)号：US07761192B2

公开(公告)日：2010-07-20

申请号：US11636492

申请日：2006-12-11

Applicant: Ching-Yu Lo

Inventor： Ching-Yu Lo

IPC: G05D13/00 ,  G05B15/00 ,  H02P7/08 ,  H02P5/46 ,  G01P1/10 ,  H01H47/00

CPC classification number: F04D25/166

Abstract: A complex signal processing system for multiple fans is used to control the rotation of a first fan and a second fan. The speed signals of the first fan and the second fan are processed through an XOR operation to obtain a complex speed signal. In response to the complex speed signal, the speed and the operational status of the first fan and the second fan can be evaluated.

Abstract translation: 用于多个风扇的复杂信号处理系统用于控制第一风扇和第二风扇的旋转。 通过异或运算来处理第一风扇和第二风扇的速度信号以获得复合速度信号。 响应于复合速度信号，可以评估第一风扇和第二风扇的速度和操作状态。

公开(公告)号：US08736014B2

公开(公告)日：2014-05-27

申请号：US12271617

申请日：2008-11-14

Applicant: Bo-Jiun Lin ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao ,  Chen-Hua Yu

Inventor： Bo-Jiun Lin ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao ,  Chen-Hua Yu

IPC: H01L21/31

CPC classification number: H01L21/3121 ,  C23C18/1212 ,  C23C18/122 ,  C23C18/1254 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02304

Abstract: A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.

Abstract translation: 公开了一种提供改进的机械强度的半导体器件和制造方法。 半导体器件包括半导体衬底; 设置在半导体衬底上的粘附层; 以及设置在所述半导体衬底上的多孔低k膜，其中所述多孔低k膜包含致孔剂和包含至少一个Si-O-Si键合基团和至少一个桥连有机官能团的复合键合结构。