利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.016 秒)

    Charge coupled device focal plane with serial register having interdigitated electrodes
    1.
    发明授权
    Charge coupled device focal plane with serial register having interdigitated electrodes 失效
    具有串联寄存器的电荷耦合器件焦平面，具有交错电极

    公开(公告)号：US4380056A

    公开(公告)日：1983-04-12

    申请号：US236415

    申请日：1981-02-20

    申请人： William J. Parrish ,  Christopher L. Fletcher

    发明人： William J. Parrish ,  Christopher L. Fletcher

    IPC分类号： G11C19/20 ,  H01L27/148 ,  G11C13/04 ,  G11C11/42

    CPC分类号： G11C19/202 ,  H01L27/14875

    摘要： This invention improves production yield and charge transfer speed and efficiency at the detector/register interface in a focal plane array and includes a novel meander channel CCD serial register in which charge packets generated in the array are stored. The electrode edge length across which charge is transferred at each entrance to the serial register is substantially increased in this invention in comparison with the prior art, resulting in a significant improvement in charge transfer efficiency and layout simplicity. Furthermore, this invention provides symmetrical surface potential distribution, and eliminates the gap instability in charge transfer.

    摘要翻译： 本发明提高焦平面阵列中的检测器/寄存器接口处的产量和电荷传输速度和效率，并且包括其中存储阵列中产生的电荷包的新型曲折通道CCD串行寄存器。 与现有技术相比，本发明中电荷在串行寄存器的每个入口处传输的电极边缘长度显着增加，导致电荷转移效率和布局简单性的显着改进。 此外，本发明提供对称的表面电位分布，并消除电荷转移中的间隙不稳定性。

    Method for fabricating a high performance PIN focal plane structure using three handle wafers
    2.
    发明授权
    Method for fabricating a high performance PIN focal plane structure using three handle wafers 有权
    使用三个手柄晶片制造高性能PIN焦平面结构的方法

    公开(公告)号：US07504277B2

    公开(公告)日：2009-03-17

    申请号：US11248366

    申请日：2005-10-12

    申请人： Christopher L. Fletcher ,  Andrew G. Toth

    发明人： Christopher L. Fletcher ,  Andrew G. Toth

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14634 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689 ,  H01L27/1469 ,  Y10S438/977

    摘要： The present invention concerns, in part, a method for fabricating a silicon PIN detector component wherein three handle wafers are bonded to the wafer at varying points in the fabrication process. The utilization of three handle wafers during fabrication significantly ease handling concerns associated with what would otherwise be a relatively thin and fragile wafer, providing a stable and strong base for supporting those portions of the wafer that will constitute the PIN detector component. In a variant of the present invention, the third handle wafer comprises an optical element transparent in the wavelength of interest.

    摘要翻译： 本发明部分涉及一种用于制造硅PIN检测器部件的方法，其中三个处理晶片在制造过程的不同点处结合到晶片。 在制造过程中三个处理晶片的利用显着地减轻了与否将是相对薄且脆弱的晶片相关联的处理问题，为构成PIN检测器部件的晶片的那些部分提供了稳定和坚固的基底。 在本发明的变型中，第三处理晶片包括在感兴趣的波长下透明的光学元件。

    Low power current input delta-sigma ADC using injection FET reference
    3.
    发明授权
    Low power current input delta-sigma ADC using injection FET reference 有权
    使用注入FET参考的低功率电流输入Δ-ΣADC

    公开(公告)号：US06977601B1

    公开(公告)日：2005-12-20

    申请号：US10769111

    申请日：2004-01-29

    申请人： Christopher L. Fletcher ,  Martins Skele

    发明人： Christopher L. Fletcher ,  Martins Skele

    IPC分类号： H03M3/00 ,  H03M3/02

    CPC分类号： H03M3/32 ,  H03M3/39 ,  H03M3/43 ,  H03M3/456 ,  H03M3/496

    摘要： A low power delta-sigma analog to digital converter 10 for converting current mode signals without an amplifier includes an integration capacitor 26, a comparator 30, and a first switch 24 in parallel with one another and coupled to an integration node 28. A FET 20 and the first switch are disposed in series between a dump capacitor 25 and the integration node. A second switch 27 operates to discharge the dump capacitor, and an output of the comparator controls both switches in opposition. Preferably, no op-amps are included in the circuit, and current is supplied by an imaging component 5. In a first comparator state, the first capacitor charges, the first switch is open and the second switch is closed, and the dump capacitor discharges. In a comparator second state, the first switch is closed and the second switch is open, and the integration capacitor transfers a fixed amount of charge into the dump capacitor through an injection FET operating in saturation.

    摘要翻译： 用于在没有放大器的情况下转换电流模式信号的低功率Δ-Σ模数转换器10包括彼此并联并耦合到积分节点28的积分电容器26，比较器30和第一开关24。 并且第一开关串联设置在卸载电容器25和集成节点之间。 第二开关27用于对卸载电容器进行放电，并且比较器的输出端对置地控制两个开关。 优选地，电路中不包括运算放大器，并且电流由成像部件5提供。在第一比较器状态下，第一电容器充电，第一开关断开，第二开关闭合，并且转储电容器放电 。 在比较器第二状态下，第一开关闭合，第二开关断开，积分电容通过饱和运行的注入FET将固定量的电荷转移到转储电容器中。

    Monolithic microelectronic array structure having substrate islands and its fabrication
    4.
    发明授权
    Monolithic microelectronic array structure having substrate islands and its fabrication 失效
    具有衬底岛的单片微电子阵列结构及其制造

    公开(公告)号：US06455931B1

    公开(公告)日：2002-09-24

    申请号：US09859618

    申请日：2001-05-15

    申请人： William J. Hamilton, Jr. ,  Michael Ray ,  Eli E. Gordon ,  Christopher L. Fletcher ,  Ronald W. Berry

    发明人： William J. Hamilton, Jr. ,  Michael Ray ,  Eli E. Gordon ,  Christopher L. Fletcher ,  Ronald W. Berry

    IPC分类号： H01L2334

    CPC分类号： H01L27/14683 ,  H01L27/14601 ,  H01L27/14643 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A monolithic microelectronic array structure includes a microelectronic integrated circuit array having a first plurality of microelectronic integrated circuit elements each deposited on a front side of a substrate. The substrates are physically discontinuous so that each substrate comprises a substrate island which is physically separated from the other substrate islands. The monolithic microelectronic array structure optionally includes a first plurality of input/output elements with a respective input/output element associated with and directly connected to each of the microelectronic integrated circuit elements, and a second plurality of electrically conductive interconnects extending between the microelectronic integrated circuit elements of adjacent substrate islands. The monolithic microelectronic array structure may be planar, or it may be curved.

    摘要翻译： 单片微电子阵列结构包括微电子集成电路阵列，其具有分别沉积在衬底的前侧上的第一多个微电子集成电路元件。 衬底物理不连续，使得每个衬底包括与其它衬底岛物理分离的衬底岛。 单片微电子阵列结构可选地包括具有与每个微电子集成电路元件相关联并直接连接到每个微电子集成电路元件的相应输入/输出元件的第一多个输入/输出元件，以及在微电子集成电路之间延伸的第二多个导电互连 相邻衬底岛的元素。 单片微电子阵列结构可以是平面的，或者它可以是弯曲的。

    Method for photo composition of large area integrated circuits
    5.
    发明授权
    Method for photo composition of large area integrated circuits 失效
    大面积集成电路照片组合方法

    公开(公告)号：US6136517A

    公开(公告)日：2000-10-24

    申请号：US36090

    申请日：1998-03-06

    申请人： Christopher L. Fletcher

    发明人： Christopher L. Fletcher

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70433 ,  G03F7/70475

    摘要： A method for forming very large scale integrated circuit devices employs a reticle having plural discrete image fields which may be respectively blocked off and exposed to form patterns on an integrated circuit wafer substrate. The division of the circuit pattern to be imaged into separate image fields is based on repeatable horizontal, vertical and two dimensional structures in the overall circuit pattern of the integrated circuit. By repeatedly exposing image fields corresponding to repeatable structures, the size of the integrated circuit device may be scaled without requiring similar scaling of the reticle itself. Efficient exposure of an entire wafer may be provided by having image fields including circuit patterns which include the scribe lanes which separate the integrated circuits on the wafer to be imaged.

    摘要翻译： 用于形成非常大规模的集成电路器件的方法使用具有多个离散图像场的掩模版，该掩模版可以被分别阻挡并暴露以在集成电路晶片衬底上形成图案。 将要成像的电路图案划分为单独的图像场是基于集成电路的总体电路图案中的可重复的水平，垂直和二维结构。 通过重复曝光对应于可重复结构的图像场，可以对集成电路器件的尺寸进行缩放，而不需要对光罩本身进行类似的缩放。 整个晶片的有效曝光可以通过具有包括电路图案的图像场来提供，该电路图案包括划分要被成像的晶片上的集成电路的划线。

    Multi-mode high capacity dual integration direct injection detector input circuit
    6.
    发明授权
    Multi-mode high capacity dual integration direct injection detector input circuit 有权
    多模高容量双积分直接注入检测器输入电路

    公开(公告)号：US07586074B2

    公开(公告)日：2009-09-08

    申请号：US10368121

    申请日：2003-02-17

    申请人： David J. Gulbransen ,  Christopher L. Fletcher

    发明人： David J. Gulbransen ,  Christopher L. Fletcher

    IPC分类号： H01L27/00 ,  H04N5/217 ,  H04N3/14

    CPC分类号： H04N5/3741 ,  G01J1/46 ,  H04N5/33 ,  H04N5/35554 ,  H04N5/35581 ,  H04N5/37452 ,  H04N5/378

    摘要： A unit cell (20) is disclosed that has an input node for coupling to an output of a detector (D1) of electromagnetic radiation, such as IR or visible radiation. The unit cell includes a first capacitor (CintA) switchably coupled to the input node for receiving a charge signal from the detector, and for integrating the charge signal during a first integration period, as well as a second capacitor (CintB)switchably coupled to the input node for integrating the charge signal during a second integration period. The unit cell further includes an output multiplexer (32, 34) for selectively coupling the first capacitor and the second capacitor to an output signal line (38) during respective charge signal readout periods. In the preferred embodiment a duration of the first integration period is one of greater than or less than the second integration period, and the first integration period is one of non-overlapping or overlapping with the second integration period, and vice versa. The first integration period can be interleaved with the second integration period, or vice versa.

    摘要翻译： 公开了一种具有用于耦合到诸如IR或可见辐射的电磁辐射的检测器（D1）的输出的输入节点的单元（20）。 单元单元包括可切换地耦合到输入节点的第一电容器（CintA），用于从检测器接收电荷信号，并且用于在第一积分周期期间积分电荷信号，以及第二电容器（CintB），其可切换地耦合到 输入节点，用于在第二积分周期期间对充电信号进行积分。 单元单元还包括输出多路复用器（32,34），用于在相应的充电信号读出周期期间选择性地将第一电容器和第二电容器耦合到输出信号线（38）。 在优选实施例中，第一积分周期的持续时间是大于或小于第二积分周期的持续时间，并且第一积分周期是与第二积分周期不重叠或重叠的一个，反之亦然。 第一积分周期可以与第二积分周期交错，反之亦然。

    Automatic gain control
    7.
    发明授权
    Automatic gain control 有权
    自动增益控制

    公开(公告)号：US06782063B1

    公开(公告)日：2004-08-24

    申请号：US09659853

    申请日：2000-09-12

    申请人： J. Mark Stevenson ,  Susan G. Briest ,  Jack R. Olson ,  Alan Fronk ,  Vincent K. McDonald ,  Christopher L. Fletcher ,  William H. Marn

    发明人： J. Mark Stevenson ,  Susan G. Briest ,  Jack R. Olson ,  Alan Fronk ,  Vincent K. McDonald ,  Christopher L. Fletcher ,  William H. Marn

    IPC分类号： H04L2708

    CPC分类号： H03G3/3089

    摘要： The invention provides an automatic gain control system that is implemented by digital hardware. The digital hardware determines the range of a set of digital data values, and then examines each digital data value in a sequence. An index counter increments a sample count index i each time a new digital data value is examined and determines the absolute value of the ith digital data value. The digital hardware also counts both the number j of digital data values that exceed a high percentage value of the range, and the number k of digital data values that are less than a low percentage value of the range as the digital hardware runs through the sequence. If the digital hardware determines that a digital data value is greater than the high percentage value, the ratio j/i exceeds a first threshold value, and the gain level is not set to the lowest gain level, then the gain is decreased. If the digital hardware determines that a digital data value is less than the low percentage value, the ratio k/i exceeds a second threshold value, a predetermined interval of time has elapsed, and the gain level is not set to the highest gain level, then the gain is increased.

    摘要翻译： 本发明提供一种由数字硬件实现的自动增益控制系统。 数字硬件确定一组数字数据值的范围，然后按顺序检查每个数字数据值。 每当检查新的数字数据值时，索引计数器递增样本计数索引i，并确定第i个数字数据值的绝对值。 数字硬件还计数超过范围的高百分比值的数字数据值的数量j，以及当数字硬件通过序列运行时小于范围的低百分比值的数字数据值的数量k 。 如果数字硬件确定数字数据值大于高百分比值，则比率j / i超过第一阈值，并且增益电平未被设置为最低增益电平，则增益减小。 如果数字硬件确定数字数据值小于低百分比值，则比率k / i超过第二阈值，经过预定的时间间隔，并且增益水平未被设置为最高增益水平， 那么增益就会增加。