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公开(公告)号：US6161215A
公开(公告)日：2000-12-12
申请号：US144299
申请日：1998-08-31
IPC分类号： H01L21/822 , G06F1/10 , G06F17/50 , H01L23/498 , H01L23/64 , H01L27/04
CPC分类号： G06F1/10 , G06F17/5077 , H01L23/49838 , H01L23/64 , H01L2224/17181 , H01L2924/00014 , H01L2924/15173 , H01L2924/3011 , H01L2224/0401
摘要： Signal delay and skew within an integrated circuit are minimized when 1) signals are distributed to distant points of an integrated circuit via a layer of its package, and 2) traces in the package layer are etched and treated as transmission lines. As disclosed herein, a signal is driven through a first connection between an integrated circuit and an integrated circuit package layer. The signal is then distributed to one or more additional connections between the integrated circuit and the integrated circuit package layer, by means of point-to-point transmission lines formed in the integrated circuit package layer, each of the transmission lines being terminated at one or both ends by impedances which are substantially matched to the characteristic impedance of the transmission line to which they are attached. The signal is then received into the integrated circuit through the one or more additional connections between the integrated circuit and the integrated circuit package layer.
摘要翻译： 当1）信号通过其封装层分布到集成电路的远端时，集成电路内的信号延迟和偏移被最小化，2）封装层中的迹线被蚀刻并被处理为传输线。 如本文所公开的，信号通过集成电路和集成电路封装层之间的第一连接被驱动。 然后，通过形成在集成电路封装层中的点对点传输线，将信号分配到集成电路和集成电路封装层之间的一个或多个附加连接，每条传输线以一个或多个 两端的阻抗基本上与其所连接的传输线的特性阻抗相匹配。 然后，该信号通过集成电路和集成电路封装层之间的一个或多个附加连接被接收到集成电路中。
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公开(公告)号：US07509639B2
公开(公告)日：2009-03-24
申请号：US10794995
申请日：2004-03-04
IPC分类号： G06F9/455
CPC分类号： G06F9/468 , G06F9/5077 , G06F9/545 , G06F21/53 , G06F21/575
摘要： Methods and techniques for implementing a custom execution environment (CE2) and a related loader are provided. According to one embodiment, the CE2 includes code and data sections of an application and code and data sections of a set of system services. The set of system services has direct and full control of a set of hardware resources of a computer system containing one or more processors implementing a parallel protected architecture. According to one embodiment, the system services are designed for maximum simplicity, fastest possible speed, and elimination of security vulnerabilities.
摘要翻译： 提供了实现自定义执行环境（CE2）和相关加载程序的方法和技术。 根据一个实施例，CE2包括应用程序的代码和数据部分以及一组系统服务的代码和数据部分。 该系统服务集可以直接和完全地控制包含实现并行保护架构的一个或多个处理器的计算机系统的一组硬件资源。 根据一个实施例，系统服务被设计为最大的简单性，最快的可能速度和消除安全漏洞。
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3.发明授权Method and system for deferring exceptions generated during speculative execution 失效用于推迟在投机执行期间产生的异常的方法和系统
公开(公告)号：US5692169A
公开(公告)日：1997-11-25
申请号：US324940
申请日：1994-10-18
申请人： Vinod K. Kathail , Rajiv Gupta , Bantwal R. Rau , Michael S. Schlansker , William S. Worley, Jr. , Frederic C. Amerson
发明人： Vinod K. Kathail , Rajiv Gupta , Bantwal R. Rau , Michael S. Schlansker , William S. Worley, Jr. , Frederic C. Amerson
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/30189 , G06F9/3842
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.
摘要翻译： 支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。 如果推测操作使用产生异常的推测操作的结果，则会传播该异常。 使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。 用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。 功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。 要检查延迟异常，功能单元然后读取寄存器文件。
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公开(公告)号：US4713755A
公开(公告)日：1987-12-15
申请号：US750381
申请日：1985-06-28
CPC分类号： G06F9/3812 , G06F12/0804 , G06F12/0837 , Y10S707/99934
摘要： Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.
摘要翻译： 在使用一组显式高速缓存控制指令的分层存储器的系统中维持存储器完整性。 系统中的缓存具有两个状态标志，一个有效位和一个脏位，每个信息块都被存储。 操作系统执行选定的缓存控制指令，以确保内存完整性，只要可能会危及完整性。
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公开(公告)号：US5933850A
公开(公告)日：1999-08-03
申请号：US843795
申请日：1997-04-21
CPC分类号： G06F9/3808 , G06F12/0875 , G06F9/30149 , G06F9/30178 , G06F9/322 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853 , G06F9/3863
摘要： An instruction cache which separates storage cells for instruction data from storage cells for sequence control is disclosed. Instructions are decoded prior to being stored to the instruction cache which serves a primary cache, while prior hierarchical levels of memory store instructions in an encoded form. Because the instructions have a variable-length, the instruction cache includes a next address determination circuit to determine the next instruction address. The invention is advantageous because the separation of storage cells enables a next instruction address to be generated during a fetch stage for a current instruction, thereby avoiding the need for an otherwise necessary additional decoding stage. A bypass mechanism useful for any cache following a cache miss is also disclosed.
摘要翻译： 公开了一种从用于序列控制的存储单元分离用于指令数据的存储单元的指令高速缓存。 指令在被存储到服务于主缓存的指令高速缓存之前被解码，而先前的层次级别的存储器以编码形式存储指令。 由于指令具有可变长度，所以指令高速缓存包括下一个地址确定电路以确定下一个指令地址。 本发明是有利的，因为存储单元的分离使得能够在当前指令的获取阶段期间产生下一个指令地址，从而避免了对另外必需的附加解码级的需要。 还公开了对于高速缓存未命中之后的任何高速缓存有用的旁路机制。
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6.发明授权
公开(公告)号：US4430705A
公开(公告)日：1984-02-07
申请号：US152891
申请日：1980-05-23
CPC分类号： G06F12/0615 , G06F12/10 , G06F12/14
摘要： Permits one program in one address space to obtain access to data in another address space without invoking a supervisor. Each of a plurality of address spaces assigned an Address Space Number (ASN) has an associated set of address translation tables. Addressability to a second address space may be specified by a program if authorized in accordance with the entry of an authority table associated with the second address space, the entry being designated by an authorization index associated with the program.
摘要翻译： 在一个地址空间中允许一个程序来访问另一个地址空间中的数据，而不调用主管。 分配了地址空间编号（ASN）的多个地址空间中的每一个具有一组相关的地址转换表。 如果根据与第二地址空间相关联的权限表的条目进行授权，程序可以指定对第二地址空间的可寻址性，该条目由与该程序相关联的授权索引指定。
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7.发明授权Method and system for protecting a computer system from denial-of-service attacks and other deleterious resource-draining phenomena related to communications 有权保护计算机系统免受拒绝服务攻击和其他与通信有关的有害资源排放现象的方法和系统公开(公告)号：US08341727B2
公开(公告)日：2012-12-25
申请号：US12075600
申请日：2008-03-10
IPC分类号： G06F15/173
CPC分类号： H04L63/1458 , H04L63/02
摘要： Embodiments of the present invention include a variety of different integrated, multi-tiered methods and systems for preventing various types of attacks on computer systems, including denial-of-service attacks and SYN-flood attacks. Components of these integrated methods and systems include probabilistic packet droppers, packet-rate throttles, resource controls, automated firewalls, and efficient connection-state-information storage in memory resources and connection-state-information distribution in order to prevent draining of sufficient communications-related resources within a computer system to seriously degrade or disable electronics communications components within the computer system.
摘要翻译： 本发明的实施例包括用于防止对计算机系统的各种攻击的各种不同的集成的多层方法和系统，包括拒绝服务攻击和SYN洪泛攻击。 这些集成方法和系统的组件包括概率分组丢弃器，分组速率节流，资源控制，自动防火墙以及存储器资源中的有效连接状态信息存储和连接状态信息分发，以防止排出足够的通信 - 计算机系统内的相关资源，以严重降低或禁用计算机系统内的电子通信组件。
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公开(公告)号：US5689653A
公开(公告)日：1997-11-18
申请号：US384308
申请日：1995-02-06
CPC分类号： G06F9/30043 , G06F15/8084 , G06F9/30036 , G06F9/3455 , G06F9/383
摘要： The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.
摘要翻译： 通过提供一个或多个向量缓冲器来减轻计算机系统的操作码带宽限制。 数据在存储器和处理器寄存器之间使用向量缓冲区在两部分进程中传输。 在第一部分中，向量请求指令通过将数据存储在识别存储器中的一组数据元素（矢量）的控制寄存器中来发起数据的缓冲。 当识别信息被加载到控制寄存器中时，向量预取控制器在存储器和向量缓冲器之间传送向量的元素。 在第二部分中，向量元素操作指令将矢量的下一个元素传送到矢量缓冲器和指定的处理器寄存器之间，用于算术或逻辑运算。
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9.发明授权System for exception recovery using a conditional substitution instruction which inserts a replacement result in the destination of the excepting instruction 失效使用条件替换指令进行异常恢复的系统，该指令将替换结果插入到除外指令的目的地
公开(公告)号：US5596733A
公开(公告)日：1997-01-21
申请号：US361874
申请日：1994-12-22
CPC分类号： G06F9/30076 , G06F11/0721 , G06F11/0793 , G06F9/3861 , G06F9/3877
摘要： A conditional substitution instruction is provided in an instruction set of a computer system to correct exceptions occurring during run-time. The conditional substitution instruction can be executed concurrently in a pipelined computer system with a potentially excepting instruction, or simultaneously in a wide computer system. The conditional substitution instruction substitutes a default value for the result of the potentially excepting instruction if the potentially excepting instruction produces one or more specified exceptions.
摘要翻译： 在计算机系统的指令集中提供条件替换指令，以纠正在运行期间发生的异常。 条件替换指令可以在具有潜在的除外指令的流水线计算机系统中同时执行，也可以在宽计算机系统中同时执行。 如果潜在的除外指令产生一个或多个指定的异常，条件替换指令将代替潜在的除外指令的结果的默认值。
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公开(公告)号：US4649478A
公开(公告)日：1987-03-10
申请号：US750626
申请日：1985-06-28
CPC分类号： G06F7/48 , G06F7/4991
摘要： Apparatus is provided which interrupts arithmetic and logical operations defined by a major opcode instruction if the resultant overflows its defined length. One major opcode defines the arithmetic and logical operations between two operands in registers and the result, zero, one, the generated condition or first operand is stored in a register.
摘要翻译： 提供了如果结果溢出其定义的长度，则中断由主要操作码指令定义的算术和逻辑运算的装置。 一个主要操作码定义了寄存器中两个操作数之间的算术和逻辑运算，结果为零，一个，生成的条件或第一个操作数存储在一个寄存器中。
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