公开(公告)号：US07183220B1

公开(公告)日：2007-02-27

申请号：US09677478

申请日：2000-10-02

申请人： Guy T. Blalock ,  David S. Becker ,  Kevin G. Donohoe

发明人： Guy T. Blalock ,  David S. Becker ,  Kevin G. Donohoe

IPC分类号： H01L21/302

CPC分类号： H01J37/32862 ,  H01L21/31116

摘要： A plasma etching method includes forming a polymer comprising carbon and a halogen over at least some internal surfaces of a plasma etch chamber. After forming the polymer, plasma etching is conducted using a gas which is effective to etch polymer from chamber internal surfaces. In one implementation, the gas has a hydrogen component effective to form a gaseous hydrogen halide from halogen liberated from the polymer. In one implementation, the gas comprises a carbon component effective to getter the halogen from the etched polymer. In another implementation, a plasma etching method includes positioning a semiconductor wafer on a wafer receiver within a plasma etch chamber. First plasma etching of material on the semiconductor wafer occurs with a gas comprising carbon and a halogen. A polymer comprising carbon and the halogen forms over at least some internal surfaces of the plasma etch chamber during the first plasma etching. After the first plasma etching and with the wafer on the wafer receiver, second plasma etching is conducted using a gas effective to etch polymer from chamber internal surfaces and getter halogen liberated from the polymer to restrict further etching of the material on the semiconductor wafer during the second plasma etching. The first and second plasma etchings are ideally conducted at subatmospheric pressure with the wafer remaining in situ on the receiver intermediate the first and second etchings, and with the chamber maintained at some subatmospheric pressure at all time intermediate the first and second plasma etchings.

摘要翻译： 等离子体蚀刻方法包括在等离子体蚀刻室的至少一些内表面上形成包含碳和卤素的聚合物。 在形成聚合物之后，使用有效地从室内表面蚀刻聚合物的气体进行等离子体蚀刻。 在一个实施方案中，气体具有有效地从从聚合物释放的卤素形成气态卤化氢的氢组分。 在一个实施方案中，气体包括有效地从蚀刻的聚合物中吸收卤素的碳组分。 在另一个实施方案中，等离子体蚀刻方法包括将半导体晶片定位在等离子体蚀刻室内的晶片接收器上。 半导体晶片上的材料的等离子体蚀刻首先用包含碳和卤素的气体进行。 在第一等离子体蚀刻期间，包含碳和卤素的聚合物在等离子体蚀刻室的至少一些内表面上形成。 在第一等离子体蚀刻和晶片接收器上的晶片之后，使用有效地从腔室内表面蚀刻聚合物的气体和从聚合物释放的吸气剂卤素来进行第二等离子体蚀刻，以限制在半导体晶片期间进一步蚀刻半导体晶片上的材料 第二等离子体蚀刻。 第一和第二等离子体蚀刻理想地在低于大气压的压力下进行，晶片在接收器上原位保留在第一和第二蚀刻物的中间，并且室在所有时间保持在一些低于大气压的压力下，介于第一和第二等离子体蚀刻之间。

公开(公告)号：US06958297B2

公开(公告)日：2005-10-25

申请号：US10445073

申请日：2003-05-23

申请人： David S. Becker ,  Bradley J. Howard ,  Kevin G. Donohoe

发明人： David S. Becker ,  Bradley J. Howard ,  Kevin G. Donohoe

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/768

CPC分类号： H01J37/321 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76804

摘要： A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0.3 micron. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen under conditions effective to produce at least that portion of the one feature pattern in the feature layer to have a sidewall taper, if any, of less than or equal to 5° and an organic masking layer top outer surface roughness proximate the feature pattern at a conclusion of the etching segment which is characterizable by an average value less than 100 Angstroms. Other implementations are also contemplated.

摘要翻译： 图案化的有机掩模层形成在要蚀刻的特征层的外侧。 它具有至少一个具有小于或等于0.3微米的最小特征尺寸的特征图案。 使用掩模层作为掩模将特征图案等离子体蚀刻到特征层中。 等离子体蚀刻包括使用蚀刻气体的至少一个蚀刻段，所述蚀刻气体包括一种包含碳，氢和至少一种卤素的气体化合物，该条件有效地产生至少该特征层中的一个特征图案的该部分具有侧壁锥形， 如果有的话，小于或等于5°的有机掩蔽层顶部外表面粗糙度，在蚀刻段结束时靠近特征图案，其特征在于平均值小于100埃。 还考虑了其​​他实施方案。

公开(公告)号：US06451678B1

公开(公告)日：2002-09-17

申请号：US09724885

申请日：2000-11-27

申请人： David S. Becker

发明人： David S. Becker

IPC分类号： H01L213205

CPC分类号： H01L21/76805 ,  H01L21/76816

摘要： A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

摘要翻译： 从半导体晶片形成用于半导体器件的晶体管的方法包括：形成在所述前部和所述晶片的背面的第一氮化物层，以及在所述前部和所述晶片的背面和在所述第一氮化物层上的第二氮化物层。 在晶片的前面形成第一抗蚀剂层，并且暴露出晶片前面的第二氮化物层的至少一部分。 从晶片的背面去除第一和第二氮化物层，同时移除在晶片前面的第二氮化物层的暴露部分的至少一部分。 接下来，形成第二层抗蚀剂，留下暴露的第一氮化物层的至少一部分。 最后，蚀刻第一氮化物层的暴露部分。

公开(公告)号：US06342165B1

公开(公告)日：2002-01-29

申请号：US09619101

申请日：2000-07-19

申请人： Kevin G. Donohoe ,  David S. Becker

发明人： Kevin G. Donohoe ,  David S. Becker

IPC分类号： H01L213065

CPC分类号： H01L21/31116

摘要： A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added. A variant of the inventive etch process employing only CHF3 during a second phase thereof may be useful in providing a “punch” or dimple at the contact bottom extending into the pristine substrate silicon under the BPSG and, optionally, other layers, and can be used to etch through both BPSG layers and nitride films to contact a word line (or the like) thereunder wherein the contact so formed has a reduced taper as it passes through the nitride film above the word line, resulting in a desirable, larger contact dimension. The system chamber temperature is defined and controlled at the roof over the wafer and the ring surrounding the wafer, the roof being held at a temperature of about 115° C. to 150° C. and preferably about 140° C., and the ring at about 200° C. to 250° C., and preferably at about 200° C. The temperature of the chuck supporting the wafer is maintained at between about −10° C. and +30° C. Chamber pressure is maintained at least at about >5 mTorr, preferably ≧20 mTorr, and most preferably between about 20 and 65 mTorr.

摘要翻译： 用于在低流量和压力下使用两个主要蚀刻剂蚀刻BPSG的等离子体蚀刻工艺，以及蚀刻室内的相对低温环境，其包括硅形式的氟清除剂。 两种主要的蚀刻剂气体是CHF 3和CH 2 F 2，以CHF 3的约10至40sccm的量级和CH 2 F 2的约10至40sccm的流速递送。 可以添加少量，大约10sccm或更小的其他气体，如C2HF5和CF4。 本发明的在其第二阶段仅使用CHF 3的蚀刻工艺的变型可用于在BPSG和任选的其他层下在延伸到原始衬底硅中的接触底部提供“冲孔”或凹坑，并且可以使用 以蚀刻通过两个BPSG层和氮化物膜以接触其上的字线（等），其中如此形成的接触在其通过字线上方的氮化物膜时具有减小的锥度，导致期望的更大的接触尺寸。 系统室温度被限定和控制在晶片周围的屋顶和围绕晶片的环上，屋顶保持在约115℃至150℃，优选约140℃的温度，并且环 约200℃至250℃，优选约200℃。支撑晶片的卡盘的温度保持在约-10℃至+ 30℃之间。腔室压力至少保持 在约> 5mTorr，优选> = 20mTorr，最优选在约20和65mTorr之间。

公开(公告)号：US06153501A

公开(公告)日：2000-11-28

申请号：US82083

申请日：1998-05-20

申请人： David S. Becker

发明人： David S. Becker

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76805 ,  H01L21/76816

摘要： A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

公开(公告)号：US6080672A

公开(公告)日：2000-06-27

申请号：US915386

申请日：1997-08-20

申请人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

发明人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

IPC分类号： H01L21/316 ,  H01L21/60 ,  H01L21/8242 ,  H01L21/00

CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/316 ,  H01L21/31625

摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.

摘要翻译： 根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。 该方法包括以下步骤。 在集成电路上形成栅极堆叠。 在栅叠层的侧壁上形成间隔物。 在集成电路上形成绝缘膜。 绝缘膜平坦化。 最后，通过平坦化绝缘膜形成栅极接触开口。 在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。 在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。 因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。 在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。 因此，本发明不需要具有相当大的深度场的光刻设备。 在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。 然后，通过附加电介质形成栅极和位线接触开口。 最后，栅极和位线触点形成为与栅极堆叠自对准。 该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。 因此，位线接触不能无意中连接到用作字线的栅极堆叠。 此连接可能会禁用集成电路。

公开(公告)号：US5869403A

公开(公告)日：1999-02-09

申请号：US818629

申请日：1997-03-14

申请人： David S. Becker ,  Mark E. Jost

发明人： David S. Becker ,  Mark E. Jost

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76802 ,  H01L21/31111 ,  H01L21/31144

摘要： A semiconductor processing method of forming a contact opening to a substrate includes forming at least one conductive line over the substrate adjacent a substrate contact area to which electrical connection is to be made. A first oxide layer is formed over the substrate to cover at least part of the contact area. A second oxide layer is formed over the first oxide layer and is formed from a different oxide than the first oxide layer. A first etch is conducted over the contact area and through the second oxide layer to a degree sufficient to leave at least a portion of the first oxide layer over the contact area. A second etch is conducted to a degree sufficient to remove substantially all of the first oxide layer left behind and to remove a desired amount of the second oxide layer laterally outwardly of the contact area. According to one preferred aspect of the invention, the first oxide layer is formed from decomposition of tetraethyloxysilane (TEOS) and the second oxide layer comprises borophosphosilicate glass (BPSG). According to another preferred aspect of the invention, the second etch is an isotropic etch using an aqueous solution comprising fluorine having less than or equal to about 10% by weight of an etch rate changing surfactant which etches the second oxide layer at a slower rate than the first oxide layer.

公开(公告)号：US5498570A

公开(公告)日：1996-03-12

申请号：US306907

申请日：1994-09-15

申请人： David S. Becker

发明人： David S. Becker

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76805 ,  H01L21/76816 ,  Y10S438/928

摘要： A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

公开(公告)号：US5286344A

公开(公告)日：1994-02-15

申请号：US898505

申请日：1992-06-15

申请人： Guy Blalock ,  David S. Becker ,  Fred Roe

发明人： Guy Blalock ,  David S. Becker ,  Fred Roe

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/31116 ,  H01L21/76802

摘要： More specifically, a process is provided for etching a multilayer structure to form a predetermined etched pattern therein. The subject process comprises providing the multilayer structure having a plurality of structural layers. The structural layers of the multilayer structure comprise a silicon dioxide outer layer on an underlying silicon nitride stop layer. Then, a chemical etchant protective layer is formed on a major surface of the multilayer structure having a predetermined pattern of openings, thereby exposing areas of the silicon dioxide outer layer corresponding to the predetermined pattern of openings. The exposed areas of the silicon dioxide outer layer are then etched down to the silicon nitride stop layer, at a high SiO.sub.2 etch rate and at a high level of selectivity of the SiO.sub.2 etch rate with respect to the Si.sub.3 N.sub.4 etch rate, with a fluorinated chemical etchant system. The fluorinated chemical etchant system includes an etchant material and an additive material. The additive material comprises a fluorocarbon material in which the number of hydrogen atoms is equal to or greater than the number of fluorine atoms. The etching step forms a substantially predetermined etch pattern in the silicon dioxide outer layer in which the contact sidewalls of said SiO.sub.2 outer layer are substantially upright.

摘要翻译： 更具体地，提供了用于蚀刻多层结构以在其中形成预定蚀刻图案的工艺。 本发明的方法包括提供具有多个结构层的多层结构。 多层结构的结构层包括在下面的氮化硅阻挡层上的二氧化硅外层。 然后，在具有预定开口图案的多层结构的主表面上形成化学蚀刻剂保护层，从而暴露对应于预定图案开口的二氧化硅外层的区域。 然后将二氧化硅外层的暴露区域以高SiO 2蚀刻速率和相对于Si 3 N 4蚀刻速率的SiO 2蚀刻速率的高选择性，以氟化化学品的方式蚀刻到氮化硅阻挡层 蚀刻系统 氟化学蚀刻剂系统包括蚀刻剂材料和添加剂材料。 添加剂材料包括其中氢原子数等于或大于氟原子数的氟碳材料。 蚀刻步骤在二氧化硅外层中形成基本上预定的蚀刻图案，其中所述SiO 2外层的接触侧壁基本上是直立的。

公开(公告)号：US5252517A

公开(公告)日：1993-10-12

申请号：US988626

申请日：1992-12-10

申请人： Guy T. Blalock ,  David S. Becker

发明人： Guy T. Blalock ,  David S. Becker

IPC分类号： H01L21/8242 ,  H01L21/28

CPC分类号： H01L27/10852 ,  Y10S148/05 ,  Y10S438/911

摘要： The method of the present invention introduces a fabrication method for providing capacitor cell polysilicon isolation from a polysilicon contact plug in a semiconductor fabrication process, by providing a contact opening through a first insulating layer, the cell polysilicon layer, and a second insulating layer, thereby exposing patterned edges of the cell polysilicon and providing access to an underlying diffusion area. The contact opening is then filled with a conductively doped polysilicon and an upper portion the polysilicon filler is removed until its top surface is recessed below the bottom surface of the cell polysilicon. Next, the cell polysilicon's patterned edges and the top of the first conductive material are oxidized which is followed by an anisotropic etch to remove the oxide only from the top of the polysilicon filler while retaining a major portion of the oxide on the cell polysilicon's patterned edges. Finally, the contact opening is refilled with conductively doped polysilicon.

摘要翻译： 本发明的方法通过提供通过第一绝缘层，单元多晶硅层和第二绝缘层的接触开口，介绍了在半导体制造工艺中从多晶硅接触插塞提供电容器单元多晶硅隔离的制造方法，由此 暴露单元多晶硅的图案化边缘并提供对底层扩散区域的访问。 然后用导电掺杂多晶硅填充接触开口，并且去除多晶硅填料的上部，直到其顶表面凹陷在电池多晶硅的底表面下方。 接下来，电池多晶硅的图案化边缘和第一导电材料的顶部被氧化，随后进行各向异性蚀刻以仅从多晶硅填料的顶部除去氧化物，同时将氧化物的主要部分保留在电池多晶硅的图案化边缘 。 最后，接触开口用导电掺杂多晶硅再填充。