利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

273 条记录 (耗时 0.03 秒)

    Self-aligned contact formation for semiconductor devices
    1.
    发明授权
    Self-aligned contact formation for semiconductor devices 有权
    用于半导体器件的自对准接触形成

    公开(公告)号：US06207571B1

    公开(公告)日：2001-03-27

    申请号：US09515804

    申请日：2000-02-29

    申请人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

    发明人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

    IPC分类号： H01L2100

    CPC分类号： H01L27/10894 ,  H01L21/316 ,  H01L21/31625 ,  H01L21/76897

    摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.

    摘要翻译： 根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。 该方法包括以下步骤。 在集成电路上形成栅极堆叠。 在栅叠层的侧壁上形成间隔物。 在集成电路上形成绝缘膜。 绝缘膜平坦化。 最后，通过平坦化绝缘膜形成栅极接触开口。 在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。 在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。 因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。 在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。 因此，本发明不需要具有相当大的深度场的光刻设备。 在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。 然后，通过附加电介质形成栅极和位线接触开口。 最后，栅极和位线触点形成为与栅极堆叠自对准。 该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。 因此，位线接触不能无意中连接到用作字线的栅极堆叠。 此连接可能会禁用集成电路。

    Self-aligned contact formation for semiconductor devices
    2.
    发明授权
    Self-aligned contact formation for semiconductor devices 失效
    用于半导体器件的自对准接触形成

    公开(公告)号：US6080672A

    公开(公告)日：2000-06-27

    申请号：US915386

    申请日：1997-08-20

    申请人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

    发明人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

    IPC分类号： H01L21/316 ,  H01L21/60 ,  H01L21/8242 ,  H01L21/00

    CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/316 ,  H01L21/31625

    摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.

    摘要翻译： 根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。 该方法包括以下步骤。 在集成电路上形成栅极堆叠。 在栅叠层的侧壁上形成间隔物。 在集成电路上形成绝缘膜。 绝缘膜平坦化。 最后，通过平坦化绝缘膜形成栅极接触开口。 在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。 在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。 因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。 在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。 因此，本发明不需要具有相当大的深度场的光刻设备。 在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。 然后，通过附加电介质形成栅极和位线接触开口。 最后，栅极和位线触点形成为与栅极堆叠自对准。 该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。 因此，位线接触不能无意中连接到用作字线的栅极堆叠。 此连接可能会禁用集成电路。

    Method of forming contact plugs
    3.
    发明授权
    Method of forming contact plugs 失效
    形成接触塞的方法

    公开(公告)号：US5858865A

    公开(公告)日：1999-01-12

    申请号：US569838

    申请日：1995-12-07

    申请人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

    发明人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

    IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/3205

    CPC分类号： H01L27/10888 ,  H01L21/28 ,  H01L21/768 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/978

    摘要： Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.

    摘要翻译： 在集成电路中，具有不延伸在栅极/字线氮化物的高度之上的高度的接触插塞仍然设置有相对较大的接触面积或着陆焊盘，其明显大于接触插塞电接触的源极/漏极区域 连接的。 用于制造本发明接触塞的方法包括（1）在氮化物间隔物形成蚀刻期间使用氮化物刻面蚀刻（a）或（b）在BPSG蚀刻期间; （2）使用（a）各向同性光致抗蚀剂蚀刻或部分除去中的至少一种来窄化栅极/字线氮化物之上的BPSG间隔区，以及（b）氮化物步骤蚀刻以蚀刻暴露于栅极/字线氮化物的肩部区域 BPSG蚀刻; 并且（3）在任何掺杂的多晶硅插塞填充之前将BPSG层向下抛光到栅极/字线氮化物的顶部，掩蔽用于BPSG蚀刻和执行BPSG蚀刻，通过部分除去蚀刻光致抗蚀剂层，并蚀刻 栅极/字线氮化物被曝光。

    Contact plug
    4.
    发明授权
    Contact plug 有权
    接触塞

    公开(公告)号：US06469389B2

    公开(公告)日：2002-10-22

    申请号：US09567649

    申请日：2000-05-09

    申请人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

    发明人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

    IPC分类号： H01L2348

    CPC分类号： H01L27/10888 ,  H01L21/28 ,  H01L21/768 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/978 ,  H01L2924/00

    摘要： Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.

    摘要翻译： 在集成电路中，具有不延伸在栅极/字线氮化物的高度之上的高度的接触插塞仍然设置有相对较大的接触面积或着陆焊盘，其明显大于接触插塞电接触的源极/漏极区域 连接的。 用于制造本发明接触塞的方法包括（1）在氮化物间隔物形成蚀刻期间使用氮化物刻面蚀刻（a）或（b）在BPSG蚀刻期间; （2）使用（a）各向同性光致抗蚀剂蚀刻或部分除去中的至少一种来窄化栅极/字线氮化物之上的BPSG间隔区，以及（b）氮化物步骤蚀刻以蚀刻暴露于栅极/字线氮化物的肩部区域 BPSG蚀刻; 并且（3）在任何掺杂的多晶硅插塞填充之前将BPSG层向下抛光到栅极/字线氮化物的顶部，掩蔽用于BPSG蚀刻和执行BPSG蚀刻，通过部分除去蚀刻光致抗蚀剂层，并蚀刻 栅极/字线氮化物被曝光。

    Semiconductor constructions
    6.
    发明申请
    Semiconductor constructions 有权
    半导体结构

    公开(公告)号：US20050121794A1

    公开(公告)日：2005-06-09

    申请号：US11026822

    申请日：2004-12-29

    申请人： Werner Juengling ,  Kirk Prall ,  Ravi Iyer ,  Gurtej Sandhu ,  Guy Blalock

    发明人： Werner Juengling ,  Kirk Prall ,  Ravi Iyer ,  Gurtej Sandhu ,  Guy Blalock

    IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

    CPC分类号： H01L23/5222 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

    摘要翻译： 本发明包括在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

    Method of forming a resistor and integrated circuitry having a resistor construction
    7.
    发明授权
    Method of forming a resistor and integrated circuitry having a resistor construction 有权
    形成电阻器的方法和具有电阻器结构的集成电路

    公开(公告)号：US06130137A

    公开(公告)日：2000-10-10

    申请号：US170792

    申请日：1998-10-13

    申请人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    发明人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    IPC分类号： H01L21/02 ,  H01L21/20

    CPC分类号： H01L28/20

    摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

    摘要翻译： 从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。 结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。 或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。