公开(公告)号：US06207571B1

公开(公告)日：2001-03-27

申请号：US09515804

申请日：2000-02-29

申请人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

发明人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

IPC分类号： H01L2100

CPC分类号： H01L27/10894 ,  H01L21/316 ,  H01L21/31625 ,  H01L21/76897

摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.

摘要翻译： 根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。 该方法包括以下步骤。 在集成电路上形成栅极堆叠。 在栅叠层的侧壁上形成间隔物。 在集成电路上形成绝缘膜。 绝缘膜平坦化。 最后，通过平坦化绝缘膜形成栅极接触开口。 在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。 在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。 因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。 在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。 因此，本发明不需要具有相当大的深度场的光刻设备。 在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。 然后，通过附加电介质形成栅极和位线接触开口。 最后，栅极和位线触点形成为与栅极堆叠自对准。 该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。 因此，位线接触不能无意中连接到用作字线的栅极堆叠。 此连接可能会禁用集成电路。

公开(公告)号：US6080672A

公开(公告)日：2000-06-27

申请号：US915386

申请日：1997-08-20

申请人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

发明人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

IPC分类号： H01L21/316 ,  H01L21/60 ,  H01L21/8242 ,  H01L21/00

CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/316 ,  H01L21/31625

摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.

摘要翻译： 根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。 该方法包括以下步骤。 在集成电路上形成栅极堆叠。 在栅叠层的侧壁上形成间隔物。 在集成电路上形成绝缘膜。 绝缘膜平坦化。 最后，通过平坦化绝缘膜形成栅极接触开口。 在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。 在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。 因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。 在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。 因此，本发明不需要具有相当大的深度场的光刻设备。 在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。 然后，通过附加电介质形成栅极和位线接触开口。 最后，栅极和位线触点形成为与栅极堆叠自对准。 该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。 因此，位线接触不能无意中连接到用作字线的栅极堆叠。 此连接可能会禁用集成电路。

公开(公告)号：US5880036A

公开(公告)日：1999-03-09

申请号：US152755

申请日：1993-11-15

申请人： David S. Becker ,  Guy T. Blalock ,  Lyle D. Breiner

发明人： David S. Becker ,  Guy T. Blalock ,  Lyle D. Breiner

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00 ,  H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/76802

摘要： A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.

公开(公告)号：US07049244B2

公开(公告)日：2006-05-23

申请号：US09923058

申请日：2001-08-06

申请人： David S. Becker ,  Guy T. Blalock ,  Fred L. Roe

发明人： David S. Becker ,  Guy T. Blalock ,  Fred L. Roe

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/76802

摘要： A process for controlling the plasma etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by (1) maintaining various portions of the etch chamber at elevated temperatures, and/ox (2) using an etch chemistry having a fluorohydrocarbon gas containing at least as many hydrogen atoms as fluorine atoms, preferably CH2F2 or CH3F.

摘要翻译： 一种用于通过（1）将蚀刻室的各种部分保持在升高的温度下和/或（ox），以相对于氮化硅，特别是多层结构的高蚀刻速率和高选择性来控制二氧化硅层的等离子体蚀刻的方法 （2）使用具有至少含有至少与氟原子一样多的氢原子的氟代烃气体的蚀刻化学品，优选CH 2 2 F 2或CH 3 > F。

公开(公告)号：US6015760A

公开(公告)日：2000-01-18

申请号：US905891

申请日：1997-08-04

申请人： David S. Becker ,  Guy T. Blalock ,  Fred L. Roe

发明人： David S. Becker ,  Guy T. Blalock ,  Fred L. Roe

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/76802

摘要： A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.

公开(公告)号：US07183220B1

公开(公告)日：2007-02-27

申请号：US09677478

申请日：2000-10-02

申请人： Guy T. Blalock ,  David S. Becker ,  Kevin G. Donohoe

发明人： Guy T. Blalock ,  David S. Becker ,  Kevin G. Donohoe

IPC分类号： H01L21/302

CPC分类号： H01J37/32862 ,  H01L21/31116

摘要： A plasma etching method includes forming a polymer comprising carbon and a halogen over at least some internal surfaces of a plasma etch chamber. After forming the polymer, plasma etching is conducted using a gas which is effective to etch polymer from chamber internal surfaces. In one implementation, the gas has a hydrogen component effective to form a gaseous hydrogen halide from halogen liberated from the polymer. In one implementation, the gas comprises a carbon component effective to getter the halogen from the etched polymer. In another implementation, a plasma etching method includes positioning a semiconductor wafer on a wafer receiver within a plasma etch chamber. First plasma etching of material on the semiconductor wafer occurs with a gas comprising carbon and a halogen. A polymer comprising carbon and the halogen forms over at least some internal surfaces of the plasma etch chamber during the first plasma etching. After the first plasma etching and with the wafer on the wafer receiver, second plasma etching is conducted using a gas effective to etch polymer from chamber internal surfaces and getter halogen liberated from the polymer to restrict further etching of the material on the semiconductor wafer during the second plasma etching. The first and second plasma etchings are ideally conducted at subatmospheric pressure with the wafer remaining in situ on the receiver intermediate the first and second etchings, and with the chamber maintained at some subatmospheric pressure at all time intermediate the first and second plasma etchings.

摘要翻译： 等离子体蚀刻方法包括在等离子体蚀刻室的至少一些内表面上形成包含碳和卤素的聚合物。 在形成聚合物之后，使用有效地从室内表面蚀刻聚合物的气体进行等离子体蚀刻。 在一个实施方案中，气体具有有效地从从聚合物释放的卤素形成气态卤化氢的氢组分。 在一个实施方案中，气体包括有效地从蚀刻的聚合物中吸收卤素的碳组分。 在另一个实施方案中，等离子体蚀刻方法包括将半导体晶片定位在等离子体蚀刻室内的晶片接收器上。 半导体晶片上的材料的等离子体蚀刻首先用包含碳和卤素的气体进行。 在第一等离子体蚀刻期间，包含碳和卤素的聚合物在等离子体蚀刻室的至少一些内表面上形成。 在第一等离子体蚀刻和晶片接收器上的晶片之后，使用有效地从腔室内表面蚀刻聚合物的气体和从聚合物释放的吸气剂卤素来进行第二等离子体蚀刻，以限制在半导体晶片期间进一步蚀刻半导体晶片上的材料 第二等离子体蚀刻。 第一和第二等离子体蚀刻理想地在低于大气压的压力下进行，晶片在接收器上原位保留在第一和第二蚀刻物的中间，并且室在所有时间保持在一些低于大气压的压力下，介于第一和第二等离子体蚀刻之间。

公开(公告)号：US5252517A

公开(公告)日：1993-10-12

申请号：US988626

申请日：1992-12-10

申请人： Guy T. Blalock ,  David S. Becker

发明人： Guy T. Blalock ,  David S. Becker

IPC分类号： H01L21/8242 ,  H01L21/28

CPC分类号： H01L27/10852 ,  Y10S148/05 ,  Y10S438/911

摘要： The method of the present invention introduces a fabrication method for providing capacitor cell polysilicon isolation from a polysilicon contact plug in a semiconductor fabrication process, by providing a contact opening through a first insulating layer, the cell polysilicon layer, and a second insulating layer, thereby exposing patterned edges of the cell polysilicon and providing access to an underlying diffusion area. The contact opening is then filled with a conductively doped polysilicon and an upper portion the polysilicon filler is removed until its top surface is recessed below the bottom surface of the cell polysilicon. Next, the cell polysilicon's patterned edges and the top of the first conductive material are oxidized which is followed by an anisotropic etch to remove the oxide only from the top of the polysilicon filler while retaining a major portion of the oxide on the cell polysilicon's patterned edges. Finally, the contact opening is refilled with conductively doped polysilicon.

摘要翻译： 本发明的方法通过提供通过第一绝缘层，单元多晶硅层和第二绝缘层的接触开口，介绍了在半导体制造工艺中从多晶硅接触插塞提供电容器单元多晶硅隔离的制造方法，由此 暴露单元多晶硅的图案化边缘并提供对底层扩散区域的访问。 然后用导电掺杂多晶硅填充接触开口，并且去除多晶硅填料的上部，直到其顶表面凹陷在电池多晶硅的底表面下方。 接下来，电池多晶硅的图案化边缘和第一导电材料的顶部被氧化，随后进行各向异性蚀刻以仅从多晶硅填料的顶部除去氧化物，同时将氧化物的主要部分保留在电池多晶硅的图案化边缘 。 最后，接触开口用导电掺杂多晶硅再填充。

公开(公告)号：US06287978B1

公开(公告)日：2001-09-11

申请号：US09344277

申请日：1999-06-30

申请人： David S. Becker ,  Guy T. Blalock ,  Fred L. Roe

发明人： David S. Becker ,  Guy T. Blalock ,  Fred L. Roe

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/76802

摘要： A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.

摘要翻译： 通过将蚀刻室的各个部分保持在升高的温度，以相对于氮化硅，特别是多层结构，以高蚀刻速率和高选择性来控制二氧化硅层的蚀刻的方法。

公开(公告)号：US06277759B1

公开(公告)日：2001-08-21

申请号：US09141775

申请日：1998-08-27

申请人： Guy T. Blalock ,  David S. Becker ,  Kevin G. Donohoe

发明人： Guy T. Blalock ,  David S. Becker ,  Kevin G. Donohoe

IPC分类号： H01L213065

CPC分类号： H01J37/32862 ,  H01L21/31116

摘要： A plasma etching method includes forming a polymer comprising carbon and a halogen over at least some internal surfaces of a plasma etch chamber. After forming the polymer, plasma etching is conducted using a gas which is effective to etch polymer from chamber internal surfaces. In one implementation, the gas has a hydrogen component effective to form a gaseous hydrogen halide from halogen liberated from the polymer. In one implementation, the gas comprises a carbon component effective to getter the halogen from the etched polymer. In another implementation, a plasma etching method includes positioning a semiconductor wafer on a wafer receiver within a plasma etch chamber. First plasma etching of material on the semiconductor wafer occurs with a gas comprising carbon and a halogen. A polymer comprising carbon and the halogen forms over at least some internal surfaces of the plasma etch chamber during the first plasma etching. After the first plasma etching and with the wafer on the wafer receiver, second plasma etching is conducted using a gas effective to etch polymer from chamber internal surfaces and getter halogen liberated from the polymer to restrict further etching of the material on the semiconductor wafer during the second plasma etching. The first and second plasma etchings are ideally conducted at subatmospheric pressure with the wafer remaining in situ on the receiver intermediate the first and second etchings, and with the chamber maintained at some subatmospheric pressure at all time intermediate the first and second plasma etchings.

摘要翻译： 等离子体蚀刻方法包括在等离子体蚀刻室的至少一些内表面上形成包含碳和卤素的聚合物。 在形成聚合物之后，使用有效地从室内表面蚀刻聚合物的气体进行等离子体蚀刻。 在一个实施方案中，气体具有有效地从从聚合物释放的卤素形成气态卤化氢的氢组分。 在一个实施方案中，气体包括有效地从蚀刻的聚合物中吸收卤素的碳组分。 在另一个实施方案中，等离子体蚀刻方法包括将半导体晶片定位在等离子体蚀刻室内的晶片接收器上。 半导体晶片上的材料的等离子体蚀刻首先用包含碳和卤素的气体进行。 在第一等离子体蚀刻期间，包含碳和卤素的聚合物在等离子体蚀刻室的至少一些内表面上形成。 在第一等离子体蚀刻和晶片接收器上的晶片之后，使用有效地从腔室内表面蚀刻聚合物的气体和从聚合物释放的吸气剂卤素来进行第二等离子体蚀刻，以限制在半导体晶片期间进一步蚀刻半导体晶片上的材料 第二等离子体蚀刻。 第一和第二等离子体蚀刻理想地在低于大气压的压力下进行，晶片在接收器上原位保留在第一和第二蚀刻物的中间，并且室在所有时间保持在一些低于大气压的压力下，介于第一和第二等离子体蚀刻之间。

公开(公告)号：US5899749A

公开(公告)日：1999-05-04

申请号：US820301

申请日：1997-03-18

申请人： David S. Becker ,  Guy T. Blalock

发明人： David S. Becker ,  Guy T. Blalock

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/32136 ,  H01L21/31116 ,  H01L21/76802

摘要： A method of etching an oxide/poly/oxide sandwich structure in which both oxide layers are anisotropically etched, and the poly layer is also isotropically etched to recess the poly from the edge of the contact walls. The oxide etch can be done using oxide to nitride etch stop technology. The process is an in situ etch, that is, a single parallel plate plasma reactor is employed.

摘要翻译： 蚀刻氧化物/多晶/氧化物夹层结构的方法，其中两个氧化物层被各向异性地蚀刻，并且多层也被各向同性地蚀刻以从接触壁的边缘凹入聚合物。 可以使用氧化物到氮化物蚀刻停止技术来进行氧化物蚀刻。 该方法是原位蚀刻，即使用单个平行板等离子体反应器。