公开(公告)号：US06207571B1

公开(公告)日：2001-03-27

申请号：US09515804

申请日：2000-02-29

申请人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

发明人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

IPC分类号： H01L2100

CPC分类号： H01L27/10894 ,  H01L21/316 ,  H01L21/31625 ,  H01L21/76897

摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.

摘要翻译： 根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。 该方法包括以下步骤。 在集成电路上形成栅极堆叠。 在栅叠层的侧壁上形成间隔物。 在集成电路上形成绝缘膜。 绝缘膜平坦化。 最后，通过平坦化绝缘膜形成栅极接触开口。 在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。 在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。 因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。 在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。 因此，本发明不需要具有相当大的深度场的光刻设备。 在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。 然后，通过附加电介质形成栅极和位线接触开口。 最后，栅极和位线触点形成为与栅极堆叠自对准。 该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。 因此，位线接触不能无意中连接到用作字线的栅极堆叠。 此连接可能会禁用集成电路。

公开(公告)号：US6080672A

公开(公告)日：2000-06-27

申请号：US915386

申请日：1997-08-20

申请人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

发明人： Werner Juengling ,  Kirk Prall ,  Trung T. Doan ,  Guy T. Blalock ,  David Dickerson ,  David S. Becker

IPC分类号： H01L21/316 ,  H01L21/60 ,  H01L21/8242 ,  H01L21/00

CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/316 ,  H01L21/31625

摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.

摘要翻译： 根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。 该方法包括以下步骤。 在集成电路上形成栅极堆叠。 在栅叠层的侧壁上形成间隔物。 在集成电路上形成绝缘膜。 绝缘膜平坦化。 最后，通过平坦化绝缘膜形成栅极接触开口。 在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。 在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。 因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。 在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。 因此，本发明不需要具有相当大的深度场的光刻设备。 在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。 然后，通过附加电介质形成栅极和位线接触开口。 最后，栅极和位线触点形成为与栅极堆叠自对准。 该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。 因此，位线接触不能无意中连接到用作字线的栅极堆叠。 此连接可能会禁用集成电路。

公开(公告)号：US06743724B2

公开(公告)日：2004-06-01

申请号：US09832560

申请日：2001-04-11

申请人： Trung T. Doan ,  Guy T. Blalock ,  Mark Durcan ,  Scott G. Meikle

发明人： Trung T. Doan ,  Guy T. Blalock ,  Mark Durcan ,  Scott G. Meikle

IPC分类号： H01L21302

CPC分类号： H01L21/31053

摘要： A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.

摘要翻译： 使用改进的化学机械平面化工艺制造半导体器件的方法，用于对其上形成半导体器件的晶片的表面进行平坦化。 改进的化学机械平面化处理包括从晶片表面上的可变形涂层形成平坦的平坦表面，其填充在通过化学机械平面化工艺在表面平坦化之前的表面凹凸之间。

公开(公告)号：US5346585A

公开(公告)日：1994-09-13

申请号：US49274

申请日：1993-04-20

申请人： Trung T. Doan ,  Guy T. Blalock

发明人： Trung T. Doan ,  Guy T. Blalock

IPC分类号： H01L21/311 ,  H01L21/00

CPC分类号： H01L21/31116

摘要： A process to create a faceted (prograde) profile for an integrated circuit, in which the top corners of a layer disposed over a feature are preferentially etched, thereby creating slopes. The profile which results from the deposit of subsequent layers is more easily etched as a result of the contour imparted by the faceted edges. Since the subsequent layers are placed in the "line of sight" of the etch plasma, there are significantly fewer "stringers."

摘要翻译： 为集成电路创建刻面（前进）轮廓的过程，其中优先蚀刻设置在特征上的层的顶角，从而产生斜面。 由于由分面边缘赋予的轮廓，更容易地蚀刻由后续层的沉积产生的轮廓。 由于随后的层被放置在蚀刻等离子体的“视线”中，所以显着减少了“桁条”。

公开(公告)号：US06331488B1

公开(公告)日：2001-12-18

申请号：US08862752

申请日：1997-05-23

申请人： Trung T. Doan ,  Guy T. Blalock ,  Mark Durcan ,  Scott G. Meikle

发明人： Trung T. Doan ,  Guy T. Blalock ,  Mark Durcan ,  Scott G. Meikle

IPC分类号： H01L21302

CPC分类号： H01L21/31053

摘要： A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.

摘要翻译： 使用改进的化学机械平面化工艺制造半导体器件的方法，用于对其上形成半导体器件的晶片的表面进行平坦化。 改进的化学机械平面化处理包括从晶片表面上的可变形涂层形成平坦的平坦表面，其填充在通过化学机械平面化工艺在表面平坦化之前的表面凹凸之间。

公开(公告)号：US5416048A

公开(公告)日：1995-05-16

申请号：US049044

申请日：1993-04-16

申请人： Guy T. Blalock ,  Trung T. Doan

发明人： Guy T. Blalock ,  Trung T. Doan

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L21/465 ,  C23C14/34

CPC分类号： H01L21/76838 ,  H01L21/3213

摘要： A process for semiconductor manufacture in which the top corners of conductive features are preferentially etched compared to the etch rate of the vertical and horizontal surfaces, thereby creating a sloped (prograde) profile, i.e., facets. The material removed through the sputter etch process is oxidized and redeposited along the sides of the feature and along the surface of the substrate, thereby improving step coverage when a subsequent dielectric layer is deposited thereon.

摘要翻译： 一种用于半导体制造的方法，其中与垂直和水平表面的蚀刻速率相比，优先蚀刻导电特征的顶角，从而产生倾斜（前进）轮廓，即小平面。 通过溅射蚀刻工艺去除的材料沿着特征的侧面并且沿着衬底的表面被氧化和再沉积，从而当随后的电介质层沉积在其上时改善步骤覆盖。

公开(公告)号：US06255209B1

公开(公告)日：2001-07-03

申请号：US09376023

申请日：1999-08-19

申请人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

发明人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C16/02 ,  C23C16/0236 ,  C23C16/42 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855

摘要： Methods are provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). The methods include forming titanium in the contact. One method includes forming titanium by combining a titanium precursor in the presence of hydrogen, H2. Another method includes forming titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. A further method includes forming titanium by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen.

摘要翻译： 提供了通过化学气相沉积（CVD）在集成电路中形成接触的方法。 所述方法包括在接触中形成钛。 一种方法包括通过在氢气存在下将钛前体组合而形成钛。 另一种方法包括在氢的存在下将四氯化钛，TiCl 4组合形成钛。 另一种方法包括在氢的存在下，通过组合四（二甲基氨基）钛，Ti（N（CH 3）2）4形成钛。

公开(公告)号：US06208033B1

公开(公告)日：2001-03-27

申请号：US09377253

申请日：1999-08-19

申请人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

发明人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C16/02 ,  C23C16/0236 ,  C23C16/42 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855

摘要： Apparatus having titanium silicide and titanium formed by chemical vapor deposition (CVD) in a contact. The chemical vapor deposition includes forming titanium silicide and/or titanium by combining a titanium precursor in the presence of hydrogen, H2. The chemical vapor deposition may further include forming titanium silicide and/or titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. The chemical vapor deposition may further include forming titanium silicide and/or by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen. For production of titanium silicide, reaction of the titanium precursor may occur with a silicon precursor or a silicon source occurring as part of the contact. Use of a silicon precursor reduces depletion of a silicon base layer in the contact.

摘要翻译： 具有通过化学气相沉积（CVD）在接触中形成的钛硅化物和钛的装置。 化学气相沉积包括通过在氢气存在下将钛前体组合而形成钛硅化物和/或钛。 化学气相沉积还可以包括在氢的存在下通过组合四氯化钛TiCl 4来形成硅化钛和/或钛。 化学气相沉积可以进一步包括在氢的存在下形成硅化钛和/或通过组合四（二甲基氨基）钛（N（CH 3）2）4）。 对于硅化钛的生产，钛前体的反应可以与作为接触部分的硅前体或硅源发生。 硅前体的使用减少了接触中硅基层的耗尽。

公开(公告)号：US06472756B2

公开(公告)日：2002-10-29

申请号：US09789999

申请日：2001-02-21

申请人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

发明人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C16/02 ,  C23C16/0236 ,  C23C16/42 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855

摘要： A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

摘要翻译： 提供了一种通过化学气相沉积（CVD）在集成电路中形成接触的方法。 在一个实施方案中，在氢的存在下使钛前体和硅前体接触以形成硅化钛。 在另一个实施方案中，钛前体与硅接触以形成硅化钛。

公开(公告)号：US06171943B2

公开(公告)日：2001-01-09

申请号：US09377273

申请日：1999-08-19

申请人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

发明人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C16/02 ,  C23C16/0236 ,  C23C16/42 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855

摘要： A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

摘要翻译： 提供了一种通过化学气相沉积（CVD）在集成电路中形成接触的方法。 在一个实施方案中，在氢的存在下使钛前体和硅前体接触以形成硅化钛。 在另一个实施方案中，钛前体与硅接触以形成硅化钛。