公开(公告)号：US4432072A

公开(公告)日：1984-02-14

申请号：US336462

申请日：1981-12-31

申请人： Hu H. Chao ,  Donelli J. DiMaria

发明人： Hu H. Chao ,  Donelli J. DiMaria

IPC分类号： H01L27/112 ,  G11C14/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  G11C11/24 ,  G11C11/34

CPC分类号： G11C14/00

摘要： This invention provides improved non-volatile semiconductor memories which include a one device dynamic volatile memory circuit having a switching device, a storage capacitor and a non-volatile floating gate device disposed between the storage node and the switching device. The non-volatile floating gate device has a floating gate, a floating gate FET, a control gate and a voltage divider having first and second serially-connected capacitors, with the floating gate being disposed at the common point between the first and second capacitors. One of the capacitors includes a dual charge or electron injector structure and the capacitance of this capacitor has a value substantially less than that of the other capacitor.

摘要翻译： 本发明提供了一种改进的非易失性半导体存储器，其包括具有开关器件，存储电容器和布置在存储节点和开关器件之间的非易失性浮置栅极器件的一个器件动态易失性存储器电路。 非易失性浮动栅极器件具有浮置栅极，浮动栅极FET，控制栅极和具有第一和第二串联电容器的分压器，浮置栅极设置在第一和第二电容器之间的公共点处。 电容器中的一个包括双电荷或电子注入器结构，并且该电容器的电容值具有显着小于另一电容器的值。

公开(公告)号：US5617351A

公开(公告)日：1997-04-01

申请号：US464018

申请日：1995-06-05

申请人： Claude L. Bertin ,  Donelli J. DiMaria ,  Makoto Miyakawa ,  Yoshinori Sakaue

发明人： Claude L. Bertin ,  Donelli J. DiMaria ,  Makoto Miyakawa ,  Yoshinori Sakaue

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/7882

摘要： A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

摘要翻译： 公开了一种适用于具有直写单元能力的电可擦除可编程只读存储器（EEPROMS）的三维存储单元。 存储单元用于制造具有高集成度密度的非易失性直写EEPROM阵列。 典型的EEPROM阵列包括形成在半导体衬底中的多个细长的浅沟槽。 多个直写EEPROM单元被布置在每个细长沟槽内，使得每个EEPROM单元与相同沟槽中的另一个单元共享回调门和编程门。 优选地，设置在每个浮动栅极与其相关联的编程和调用栅极之间的富硅电介质（例如富氧氧化物）。 公开了源极扩散和隔离源扩散实施例。 此外，描述了所呈现的用于直写EEPROM阵列的各种制造方法。

公开(公告)号：US4104675A

公开(公告)日：1978-08-01

申请号：US808501

申请日：1977-06-21

申请人： Donelli J. DiMaria ,  Donald R. Young

发明人： Donelli J. DiMaria ,  Donald R. Young

IPC分类号： H01L29/417 ,  G11C16/04 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8247 ,  H01L27/088 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L45/00 ,  H01L29/34

CPC分类号： H01L21/28194 ,  G11C16/0466 ,  H01L21/31155 ,  H01L27/088 ,  H01L29/51 ,  H01L29/513 ,  H01L29/792 ,  H01L29/94 ,  H01L45/00

摘要： A graded oxide MIM or MIS structure employs band gap grading of the insulator oxide so that holes or electrons (depending on voltage bias) can be injected into the insulator oxide under moderate electric field conditions from the contact at one interface. Electron or hole injection from the opposite interface is blocked due to the larger insulator band gap near this interface. A graded oxide metal-silicon dioxide-silicon (MGOS) semiconductor structure may be fabricated by forming several pyrolytic or CVD SiO.sub.2 layers over a relatively thick thermal SiO.sub.2 layer, with the pyrolytic SiO.sub.2 layers having sequentially increasing excess Si content. This structure may also be fabricated by controlled Si ion implantation in the thermal SiO.sub.2 layer.

摘要翻译： 梯度氧化物MIM或MIS结构采用绝缘体氧化物的带隙分级，使得空穴或电子（取决于电压偏置）可以在适当电场条件下从一个界面处的触点注入到绝缘体氧化物中。 由于在该界面附近较大的绝缘体带隙，来自相对界面的电子或空穴注入被阻挡。 可以通过在相对较厚的热SiO 2层上形成几个热解或CVD SiO 2层来制造分级氧化物金属 - 二氧化硅 - 硅（MGOS）半导体结构，其中热解SiO 2层具有相继增加的过量Si含量。 该结构也可以通过在SiO 2层中的受控Si离子注入来制造。

公开(公告)号：US5468663A

公开(公告)日：1995-11-21

申请号：US405128

申请日：1995-03-16

申请人： Claude L. Bertin ,  Donelli J. DiMaria ,  Makoto Miyakawa ,  Yoshinori Sakaue

发明人： Claude L. Bertin ,  Donelli J. DiMaria ,  Makoto Miyakawa ,  Yoshinori Sakaue

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/7882

摘要： A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

摘要翻译： 公开了一种适用于具有直写单元能力的电可擦除可编程只读存储器（EEPROMS）的三维存储单元。 存储单元用于制造具有高集成度密度的非易失性直写EEPROM阵列。 典型的EEPROM阵列包括形成在半导体衬底中的多个细长的浅沟槽。 多个直写EEPROM单元被布置在每个细长沟槽内，使得每个EEPROM单元与相同沟槽中的另一个单元共享回调门和编程门。 优选地，设置在每个浮动栅极与其相关联的编程和调用栅极之间的富硅电介质（例如富氧氧化物）。 公开了源极扩散和隔离源扩散实施例。 此外，描述了所呈现的用于直写EEPROM阵列的各种制造方法。

公开(公告)号：USRE31083E

公开(公告)日：1982-11-16

申请号：US213537

申请日：1980-12-05

申请人： Roger F. DeKeersmaecker ,  Donelli J. DiMaria ,  Donald R. Young

发明人： Roger F. DeKeersmaecker ,  Donelli J. DiMaria ,  Donald R. Young

IPC分类号： H01L29/51 ,  H01L29/792

CPC分类号： H01L29/513 ,  H01L29/792

摘要： New non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structures are described. With the graded or stepped insulator, electrons or holes can be injected from the gate electrode at low to moderate applied fields. The carriers flow under the applied field into a wide energy band gap insulator having a prescribed charge trapping layer. This layer captures and stores electrons (write operation) or holes (erase operation) with 100% efficiency.

公开(公告)号：US4217601A

公开(公告)日：1980-08-12

申请号：US12279

申请日：1979-02-15

申请人： Roger F. DeKeersmaecker ,  Donelli J. DiMaria ,  Donald R. Young

发明人： Roger F. DeKeersmaecker ,  Donelli J. DiMaria ,  Donald R. Young

IPC分类号： H01L27/112 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/34

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792 ,  Y10S148/082

摘要： New non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structures are described. With the graded or stepped insulator, electrons or holes can be injected from the gate electrode at low to moderate applied fields. The carriers flow under the applied field into a wide energy band gap insulator having a prescribed charge trapping layer. This layer captures and stores electrons (write operation) or holes (erase operation) with 100% efficiency.

摘要翻译： 描述了由分级或阶梯式能带隙绝缘体MIM或MIS结构制造的新的非易失性存储器件。 对于分级或阶梯绝缘体，可以在低到中等施加的场下从栅电极注入电子或空穴。 载体在施加的场下流动到具有规定的电荷捕获层的宽能带隙绝缘体中。 该层以100％的效率捕获并存储电子（写入操作）或空穴（擦除操作）。

公开(公告)号：US5467305A

公开(公告)日：1995-11-14

申请号：US850734

申请日：1992-03-12

申请人： Claude L. Bertin ,  Donelli J. DiMaria ,  Makoto Miyakawa ,  Yoshinori Sakaue

发明人： Claude L. Bertin ,  Donelli J. DiMaria ,  Makoto Miyakawa ,  Yoshinori Sakaue

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C14/00

CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/7882

摘要： A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

摘要翻译： 公开了一种适用于具有直写单元能力的电可擦除可编程只读存储器（EEPROMS）的三维存储单元。 存储单元用于制造具有高集成度密度的非易失性直写EEPROM阵列。 典型的EEPROM阵列包括形成在半导体衬底中的多个细长的浅沟槽。 多个直写EEPROM单元被布置在每个细长沟槽内，使得每个EEPROM单元与相同沟槽中的另一个单元共享回调门和编程门。 优选地，设置在每个浮动栅极与其相关联的编程和调用栅极之间的富硅电介质（例如富氧氧化物）。 公开了源极扩散和隔离源扩散实施例。 此外，描述了所呈现的用于直写EEPROM阵列的各种制造方法。

公开(公告)号：US4471471A

公开(公告)日：1984-09-11

申请号：US336463

申请日：1981-12-31

申请人： Donelli J. DiMaria

发明人： Donelli J. DiMaria

IPC分类号： G11C14/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  G11C11/24

CPC分类号： G11C14/00 ,  H01L29/7882

摘要： Juxtaposing, on a common p-type substrate, an array of field effect transistor memory cells each including a random access memory dynamic RAM device comprising a floating gate portion and a storage node, and each including also a non-volatile unit comprising a double electron injector structure (DEIS) adjacent the floating gate portion, but remote from the storage node, provides a simple, low current dynamic random access memory array with non-volatile restart capability in case of power interruption.The non-volatile unit in each memory cell shares the control gate and substrate in common with the dynamic RAM device and thus shares access to the floating gate but is remote from the storage node. Situated between the floating gate and the substrate is a silicon-rich DEIS stack. During normal operation, the device functions as a dynamic RAM device. When non-volatile storage is required, electrons are written into the floating gate by raising the voltage on the control gate. This injects electrons into an insulating layer in the DEIS; the electrons flow to the floating gate where they are stored indefinitely. Subsequent write and erase operations are carried out by applying an appropriately polarized voltage pulse to the control gate electrode, moving electrons with respect to the floating gate portion of the RAM device.

摘要翻译： 每个场效应晶体管存储单元阵列在公共p型衬底上并置，每个场效应晶体管存储单元包括一个包括浮动栅极部分和存储节点的随机存取存储器动态RAM器件，并且每个还包括一个包含双电子 与浮动栅极部分相邻但远离存储节点的喷射器结构（DEIS）在电力中断的情况下提供具有非易失性重启能力的简单的低电流动态随机存取存储器阵列。 每个存储器单元中的非易失性单元与动态RAM设备共用控制栅极和衬底，从而共享对浮动栅极的访问，但是远离存储节点。 位于浮动栅极和基板之间的是富含硅的DEIS堆叠。 在正常操作期间，该设备用作动态RAM设备。 当需要非易失性存储时，通过提高控制栅极上的电压将电子写入浮置栅极。 这将电子注入到DEIS中的绝缘层中; 电子流到浮动栅极，无限期地存储在其中。 通过向控制栅电极施加适当极化的电压脉冲，相对于RAM器件的浮动栅极部分移动电子来执行随后的写入和擦除操作。

公开(公告)号：US4939559A

公开(公告)日：1990-07-03

申请号：US847127

申请日：1986-04-01

申请人： Donelli J. DiMaria ,  David W. Dong

发明人： Donelli J. DiMaria ,  David W. Dong

IPC分类号： H01L29/788

CPC分类号： H01L29/7882

摘要： The present invention relates to DEIS (Dual Electron Injector Structure) EAROM (Electrically Alterable Read Only Memory) devices which utilize a silicon-rich, silicon dioxide insulator between injectors which has an excess of silicon therein which is less than the excess of silicon in the silicon rich, silicon dioxide injectors. The device does not depart in any way from known DEIS EAROM devices except that the insulator layer between the injectors is rendered conductive to a desired degree by causing a compound insulator like SiO.sub.2 to be off-stoichiometry during deposition so that the resulting insulator becomes silicon rich. Alternatively, the insulator may be deposited together with another metal which renders the insulator conductive or a metallic specie may be added to the insulator by diffusion or ion implantation after the insulator is formed. The resulting conductive insulator provides a means for draining off trapped charge in the insulator resulting in a device of such improved cyclibility that the DEIS EAROM can be used as a Non-Volatile Random Access Memory (NVRAM) capable of from 10.sup.8 to greater than 10.sup.10 cycles before threshold collapse occurs. The conductive insulator is designed so that it is conductive only at high electric fields encountered during writing and erasing and highly blocking at low fields encountered during reading or storage operations.

摘要翻译： 本发明涉及DEIS（双电子注入器结构）EAROM（电可更改只读存储器）器件，其利用在其中具有过量硅的小于硅中过量的硅之间的富含硅的二氧化硅绝缘体 富硅，二氧化硅注射器。 器件不会以任何方式离开已知的DEIS EAROM器件，除了注入器之间的绝缘体层通过在沉积期间使诸如SiO 2的复合绝缘体离开化学计量而导致所需的程度，使得所得绝缘体变得富含硅 。 或者，可以在形成绝缘体之后通过扩散或离子注入将绝缘体与另一种使绝缘体导电的金属或金属物质一起沉积在绝缘体上。 所得到的导电绝缘体提供了用于排出绝缘体中捕获的电荷的装置，导致具有这种改进的可循环性的装置，DEIS EAROM可以用作能够从108到大于1010个循环的非易失性随机存取存储器（NVRAM） 在阈值崩溃之前发生。 导电绝缘体被设计成仅在写入和擦除期间遇到的高电场和在读取或存储操作期间遇到的低磁场下高度阻塞时才导电。

公开(公告)号：US4752812A

公开(公告)日：1988-06-21

申请号：US2076

申请日：1987-01-12

申请人： Maurizio Arienzo ,  Donelli J. DiMaria

发明人： Maurizio Arienzo ,  Donelli J. DiMaria

IPC分类号： H01L29/68 ,  H01L29/772 ,  H01L29/80 ,  H01L49/02

CPC分类号： H01L29/7722

摘要： A semiconductor structure that includes a semiconductor substrate; an insulating layer adjacent the substrate; a semiconductor or conductor grid adjacent the insulating layer; another insulating layer adjacent the semiconductor grid; and an injector adjacent the second insulating layer. The injector includes a layer of silicon-rich insulator material and a layer of semiconductor material adjacent the silicon-enriched material.