公开(公告)号：US5539186A

公开(公告)日：1996-07-23

申请号：US988078

申请日：1992-12-09

申请人： Anthony J. Abrami ,  Maurizio Arienzo ,  Giulio DiGiacomo ,  Gene J. Gaudenzi ,  Paul V. McLaughlin

发明人： Anthony J. Abrami ,  Maurizio Arienzo ,  Giulio DiGiacomo ,  Gene J. Gaudenzi ,  Paul V. McLaughlin

IPC分类号： H01L23/34 ,  H05B3/20 ,  H05K1/02 ,  H05K1/03 ,  H05K1/16 ,  H05K3/34 ,  H05K3/46 ,  H05B3/02

CPC分类号： H01L24/98 ,  H01L23/34 ,  H01L23/345 ,  H05B3/20 ,  H05K1/0212 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K1/167 ,  H05K2201/10151 ,  H05K2201/10674 ,  H05K2203/1115 ,  H05K2203/165 ,  H05K2203/176 ,  H05K3/3436 ,  H05K3/3494 ,  H05K3/4611 ,  H05K3/4629

摘要： A multi-layer module that has incorporated therein an additional sheet with a heat generating film resistor formed thereon. A temperature responsive controller regulates the film resistor current in order to regulate the temperature at the surface of the module. The invention is applicable to both single chip and multiple chip modules, and for multi-chip modules a plurality of discrete film resistors on a single may be used.

摘要翻译： 一种多层模块，其中结合有附加的片材，其上形成有发热膜电阻器。 温度响应控制器调节薄膜电阻器电流，以调节模块表面的温度。 本发明可应用于单芯片和多芯片模块，并且对于多芯片模块，可以使用单个多个分立的薄膜电阻器。

公开(公告)号：US5395769A

公开(公告)日：1995-03-07

申请号：US904729

申请日：1992-06-26

申请人： Maurizio Arienzo ,  David L. Harame ,  Gottlieb S. Oehrlein

发明人： Maurizio Arienzo ,  David L. Harame ,  Gottlieb S. Oehrlein

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/331

CPC分类号： H01L29/66287 ,  H01L21/3065

摘要： The present invention is a structure and method for controlling the depth of an etching process. In particular, the method and structure of the present invention creates a marker layer which resides between a layer to be etched and a protected layer. The marker layer is detected during the etch process and the etch process is controlled based on the detection of the marker layer. The marker layer has physical characteristics which are very similar to the layers being etched or protected. The marker layer has a similar lattice constant and electrical behavior to either the etched layer or the protected layer. The marker layer has very different optical properties from the etched or protected layers so that even a thin marker layer can be easily detected using in-situ ellipsometric measurements. A specific embodiment of the present invention is a layer of SiGe interposed between a thick silicon layer and a thin silicon layer. In particular, the SiGe layer has a composition of approximately 10% of germanium and has a thickness of approximately 10.ANG.. The thick silicon layer has a thickness of approximately 5,000.ANG. and the thin silicon layer has a thickness of approximately 1,000.ANG.. A method of etching the thick silicon layer, incorporating one embodiment of the present invention, is to perform a RIE process on the thick silicon layer while monitoring the RIE process with an ellipsometer. When the RIE process encounters the underlying marker layer, the ellipsometer measurements show a marked change. The marked change in the ellipsometer measurements indicate when to stop the RIE process. When the marker layer is very thin, such as 10.ANG., the RIE process is stopped immediately and the underlying thin silicon layer is not etched into. Even though the RIE process is not uniform, and parts of the marker layer will remain on the surface of the protected layer, this will not affect the electrical behavior of the resulting semiconductor device using this process. This is because the thin SiGe marker layer has electrical characteristics which are very similar to the underlying silicon layer.

公开(公告)号：US4752812A

公开(公告)日：1988-06-21

申请号：US2076

申请日：1987-01-12

申请人： Maurizio Arienzo ,  Donelli J. DiMaria

发明人： Maurizio Arienzo ,  Donelli J. DiMaria

IPC分类号： H01L29/68 ,  H01L29/772 ,  H01L29/80 ,  H01L49/02

CPC分类号： H01L29/7722

摘要： A semiconductor structure that includes a semiconductor substrate; an insulating layer adjacent the substrate; a semiconductor or conductor grid adjacent the insulating layer; another insulating layer adjacent the semiconductor grid; and an injector adjacent the second insulating layer. The injector includes a layer of silicon-rich insulator material and a layer of semiconductor material adjacent the silicon-enriched material.