公开(公告)号：US09583592B2

公开(公告)日：2017-02-28

申请号：US14697266

申请日：2015-04-27

申请人： Pan-Kwi Park ,  Dong-Suk Shin ,  Seok-Jun Won ,  Weon-Hong Kim ,  Jae-Gon Lee

发明人： Pan-Kwi Park ,  Dong-Suk Shin ,  Seok-Jun Won ,  Weon-Hong Kim ,  Jae-Gon Lee

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02332 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure.

摘要翻译： 在制造半导体器件的方法中，在基板上形成虚拟栅极结构。 在衬底上形成第一间隔层以覆盖虚拟栅极结构。 在第一间隔层上进行氮化处理。 去除与伪栅极结构相邻的衬底的上部以形成沟槽。 清洁沟槽的内壁。 形成外延层以填充沟槽。 虚拟栅极结构被栅极结构代替。

公开(公告)号：US09214530B2

公开(公告)日：2015-12-15

申请号：US14033639

申请日：2013-09-23

申请人： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

发明人： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06

CPC分类号： H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

摘要翻译： 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US20150318399A1

公开(公告)日：2015-11-05

申请号：US14600142

申请日：2015-01-20

申请人： Yeong-Jong JEONG ,  Jeong-Yun LEE ,  Geo-Myung SHIN ,  Dong-Suk SHIN ,  Si-Hyung LEE ,  Seo-Jin JEONG

发明人： Yeong-Jong JEONG ,  Jeong-Yun LEE ,  Geo-Myung SHIN ,  Dong-Suk SHIN ,  Si-Hyung LEE ,  Seo-Jin JEONG

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC分类号： H01L29/7848 ,  B82Y10/00 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/78696

摘要： A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.

摘要翻译： 一种半导体器件包括由场绝缘层限定并沿着第一方向延伸的第一多沟道有源图案，该第一多沟道有源图案包括第一部分，该第一部分具有在向上方向上进一步向上方突出的顶表面， 所述场绝缘层和所述第一部分的两侧上的第二部分，所述第二部分具有连续轮廓的侧壁和在所述场绝缘层的顶表面上向上方向突出的顶表面，并且在向上方向上突出 小于第一部分的顶表面的第一部分上的栅电极，在第一多通道有源图案的第一部分上并且沿着不同于第一方向的第二方向延伸的栅电极，以及在第一部分的第二部分上的第一源极/漏极区域 第一多通道有源图案并接触场绝缘层。

公开(公告)号：US20130320434A1

公开(公告)日：2013-12-05

申请号：US13908440

申请日：2013-06-03

申请人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

发明人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

IPC分类号： H01L29/78

CPC分类号： H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

摘要翻译： 在半导体器件中，第一有源区具有第一西格玛形状，第二有源区具有第二西格玛形状。 当垂直于衬底并将第一栅电极的侧表面通过第一区域的线被定义为第一垂直线时，当垂直于衬底并通过第二栅电极的侧表面的线 在第二区域被定义为第二垂直线时，当第一垂直线和第一沟槽之间的最短距离被定义为第一水平距离时，并且当第二垂直线和第二沟槽之间的最短距离被定义为 第二水平距离，第一水平距离和第二水平距离之间的差等于或小于1nm。

公开(公告)号：US20130169337A1

公开(公告)日：2013-07-04

申请号：US13528148

申请日：2012-06-20

申请人： Dong-Suk Shin

发明人： Dong-Suk Shin

IPC分类号： H03H11/26

CPC分类号： H03L7/089 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/0028

摘要： A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2≦A≦N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A−1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

摘要翻译： 一种相位差量化电路的延迟值控制电路，其中相位差量化电路具有二进制权重的第一至第N（N是等于或大于2的整数）延迟单元。 延迟值控制电路包括复制Ath（2 @ A @ N）延迟单元的复制延迟单元; 以及延迟控制单元，被配置为比较从延迟输入信号产生的第一输出信号与第一延迟单元的相位和从延迟输入信号而产生的第二输出信号的相位与Ath延迟单元和副本 延迟单元，并且被配置为使用比较结果来控制Ath延迟单元的延迟值。

公开(公告)号：US08450125B2

公开(公告)日：2013-05-28

申请号：US13186515

申请日：2011-07-20

申请人： Dong-Suk Shin ,  Yong-Joo Lee ,  Dong-Hyuk Kim ,  Myung-Sun Kim ,  Hoi-Sung Chung

发明人： Dong-Suk Shin ,  Yong-Joo Lee ,  Dong-Hyuk Kim ,  Myung-Sun Kim ,  Hoi-Sung Chung

IPC分类号： H01L21/66

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L22/12 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of evaluating an epitaxial growing process includes forming a mold layer on each of a plurality of substrates, forming a photoresist pattern on each mold layer, the photoresist pattern having opening portions, a total area of a bottom portion of the opening portions being different for each substrate, patterning each mold layer to expose a surface portion of the substrate to form an evaluation pattern on each substrate, evaluation patterns including opening portions corresponding to the opening portion in the photoresist pattern, determining substrate opening ratios for each substrate based on the opening portions in the evaluation pattern thereon, the substrate opening ratios being different for each substrate, performing a selective epitaxial process on each substrate to form an epitaxial layer, and evaluating characteristics of the epitaxial layer for each substrate to determine an optimal substrate opening ratio.

摘要翻译： 评价外延生长方法的方法包括在多个基板的每一个上形成模具层，在每个模具层上形成光致抗蚀剂图案，所述光致抗蚀剂图案具有开口部分，所述开口部分的底部的总面积不同 对于每个基板，图案化每个模具层以暴露基板的表面部分以在每个基板上形成评估图案，评估图案包括与光致抗蚀剂图案中的开口部分对应的开口部分，基于该基板确定每个基板的基板开口率 在其上的评估图案中的开口部分，基板开口率对于每个基板不同，在每个基板上执行选择性外延处理以形成外延层，以及评估每个基板的外延层的特性以确定最佳的基板开口率。

公开(公告)号：US08330512B2

公开(公告)日：2012-12-11

申请号：US12843568

申请日：2010-07-26

申请人： Ki Han Kim ,  Dong Suk Shin

发明人： Ki Han Kim ,  Dong Suk Shin

IPC分类号： H03L7/06

CPC分类号： H03H11/265 ,  H03L7/0816

摘要： A clock generation circuit of a semiconductor apparatus includes a first phase detection block configured to compare initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and output an initial phase difference detection signal corresponding to a comparison result; a second phase detection block configured to compare phases of the reference clock signal and the output clock signal, and output a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and configured to delay the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and output the output clock signal; and a delay control block configured to generate the control voltage which has the voltage level corresponding to the phase detection signal.

摘要翻译： 半导体装置的时钟生成电路包括第一相位检测块，其被配置为响应于操作开始信号来比较参考时钟信号和输出时钟信号的初始相位，并且输出与比较结果相对应的初始相位差检测信号 ; 第二相位检测块，被配置为比较参考时钟信号和输出时钟信号的相位，并输出与比较结果对应的相位检测信号; 响应于初始相位差检测信号在其延迟量的控制范围内确定的可变单位延迟块，并且被配置为将参考时钟信号延迟与控制电压的电压电平相对应的延迟量，并输出输出 时钟信号; 以及延迟控制块，被配置为产生具有与相位检测信号相对应的电压电平的控制电压。

公开(公告)号：US20120293225A1

公开(公告)日：2012-11-22

申请号：US13341436

申请日：2011-12-30

申请人： Dong Suk SHIN

发明人： Dong Suk SHIN

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty correction circuit includes a clock buffer configured to buffer an input clock and generate a buffer clock, a swing level conversion block configured to generate an internal clock, which transitions to levels of a sync voltage and a power supply voltage, in response to a voltage level of the buffer clock, a duty control block configured to generate duty information and frequency information by using a high pulse width and a low pulse width of the internal clock, and a current control block configured to control a time point, at which a logic value of the buffer clock transitions, in response to the duty information and the frequency information. The current control block includes a plurality of first current paths coupled in parallel to one another in order to control the time point at which the logic value of the buffer clock transitions.

摘要翻译： 一种占空比校正电路包括：时钟缓冲器，被配置为缓冲输入时钟并产生缓冲时钟;摆动电平转换模块，被配置为产生转换到同步电压和电源电压的电平的内部时钟，响应于 缓冲时钟的电压电平，配置为通过使用内部时钟的高脉冲宽度和低脉冲宽度来产生占空比信息和频率信息的占空比控制块，以及被配置为控制时间点的电流控制块， 响应于占空比信息和频率信息，缓冲时钟的逻辑值转换。 当前控制块包括彼此并联耦合的多个第一电流路径，以便控制缓冲时钟的逻辑值转变的时间点。

公开(公告)号：US08278985B2

公开(公告)日：2012-10-02

申请号：US12983177

申请日：2010-12-31

申请人： Dong Suk Shin

发明人： Dong Suk Shin

IPC分类号： H03L7/06

CPC分类号： G11C8/18 ,  G11C8/04 ,  H03L7/0812

摘要： A synchronization circuit includes a first loop circuit configured to set an initial delay time by using first initial delay information and generate a first delay signal by changing a delay time of a first input signal, a second loop circuit configured to set the initial delay time by using second initial delay information and generate a second delay signal by changing a delay time of a second input signal, a duty cycle correction unit configured to correct a duty cycle of the first delay signal by using the second delay signal, and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to an internal delay signal of the first loop circuit and the first input signal.

摘要翻译： 同步电路包括第一环路电路，其被配置为通过使用第一初始延迟信息来设置初始延迟时间，并且通过改变第一输入信号的延迟时间来产生第一延迟信号，第二环路电路被配置为将初始延迟时间设置为 使用第二初始延迟信息并通过改变第二输入信号的延迟时间来产生第二延迟信号;占空比校正单元，被配置为通过使用第二延迟信号来校正第一延迟信号的占空比，以及初始延迟监视 电路，被配置为响应于第一环路电路和第一输入信号的内部延迟信号产生第一初始延迟信息和第二初始延迟信息。

公开(公告)号：US20120223802A1

公开(公告)日：2012-09-06

申请号：US13471508

申请日：2012-05-15

申请人： Dong-suk SHIN ,  Andrew-tae KIM ,  Hong-jae SHIN

发明人： Dong-suk SHIN ,  Andrew-tae KIM ,  Hong-jae SHIN

IPC分类号： H01H85/08

CPC分类号： H01L23/5256 ,  H01L23/5258 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

摘要翻译： 本发明一般涉及半导体器件的熔丝器件，更具体地，涉及一种半导体器件的电熔丝器件。 本发明的实施例提供一种能够减少由熔丝链中的不均匀电流密度引起的编程误差的熔丝装置。 在一方面，提供一种电熔丝装置，其包括：阳极; 熔丝链路，其在所述熔丝连接件的第一侧上耦合到所述阳极; 连接到所述熔丝链的第二侧上的所述熔断体的阴极; 耦合到阴极的第一阴极接触; 以及耦合到所述阳极的第一阳极触点，所述第一阴极触点和所述第一阳极触点中的至少一个跨越所述熔断体的虚拟延伸表面设置。