公开(公告)号：US08273638B2

公开(公告)日：2012-09-25

申请号：US11968365

申请日：2008-01-02

Applicant: Jae-Bon Koo ,  Sang-Gul Lee

Inventor： Jae-Bon Koo ,  Sang-Gul Lee

IPC: C30B1/08 ,  C09K19/00

CPC classification number: H01L27/12 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/1277 ,  H01L29/78603

Abstract: Provided is a thin film transistor that may be manufactured using Metal Induced Crystallization (MIC) and method for fabricating the same. Also provided is an active matrix flat panel display using the thin film transistor, which may be created by forming a crystallization inducing metal layer below a buffer layer and diffusing the crystallization inducing metal layer. The thin film transistor may include a crystallization inducing metal layer formed on an insulating substrate, a buffer layer formed on the crystallization inducing metal layer, and an active layer formed on the buffer layer and including source/drain regions, and including polycrystalline silicon crystallized by the MIC process.

Abstract translation: 提供了可以使用金属诱导结晶（MIC）制造的薄膜晶体管及其制造方法。 还提供了使用薄膜晶体管的有源矩阵平板显示器，其可以通过在缓冲层下方形成结晶诱导金属层并扩散结晶诱导金属层来产生。 薄膜晶体管可以包括形成在绝缘基板上的结晶诱导金属层，形成在结晶诱导金属层上的缓冲层，以及形成在缓冲层上并包括源极/漏极区域的有源层，并且包括由 MIC过程。

公开(公告)号：US20100106338A1

公开(公告)日：2010-04-29

申请号：US12569270

申请日：2009-09-29

Applicant: Su-Chul NAM ,  Jeong-Hoon SHIN ,  Seung-Tae CHA ,  Jae-Gul LEE ,  Tae-Kyun KIM

Inventor： Su-Chul NAM ,  Jeong-Hoon SHIN ,  Seung-Tae CHA ,  Jae-Gul LEE ,  Tae-Kyun KIM

IPC: G06F1/28 ,  G06F17/10 ,  G06G7/63

CPC classification number: G06F1/305

Abstract: Provided is an optimized system voltage control method through coordinated control of reactive power source, which analyzes the location for reactive power compensation and the effect of applying compensation equipment by calculating the reactive power and voltage sensitivity of a power system, thus improving the voltage quality of the power system.The optimized system voltage control method includes verifying a voltage violation substation having a voltage exceeding a predetermined voltage reference value among buses of a test system on a computer program, configuring a local system with eight to ten substations with respect to the verified voltage violation substation, generating a reduced local system using a reduced local algorithm with respect to the buses within the configured local system, calculating a power flow by determining a voltage control amount for restoring the voltage of the voltage violation substation to a normal value with respect to the reduced local system, and calculating an optimization objective function value based on the voltage control amount and control operation.

Abstract translation: 提供了一种通过无功电源协调控制的优化系统电压控制方法，通过计算电力系统的无功功率和电压灵敏度来分析无功补偿的位置和施加补偿设备的效果，从而提高电力质量 电力系统。 优化的系统电压控制方法包括在计算机程序的测试系统的总线之间验证具有超过预定电压参考值的电压的电压异常变电站，配置相对于经过验证的电压异常变电站的八到十个变电站的本地系统， 使用关于所配置的本地系统内的总线的减少的本地算法来生成减少的本地系统，通过确定用于将电压违规变电站的电压恢复到相对于减小的本地的正常值的电压控制量来计算功率流 系统，并且基于电压控制量和控制操作来计算优化目标函数值。

公开(公告)号：US20050116305A1

公开(公告)日：2005-06-02

申请号：US10992645

申请日：2004-11-22

Applicant: Eui-Hoon Hwang ,  Sang-Gul Lee ,  Deuk-Jong Kim

Inventor： Eui-Hoon Hwang ,  Sang-Gul Lee ,  Deuk-Jong Kim

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L21/335 ,  H01L21/338 ,  H01L21/8232 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66757 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78675 ,  H01L29/78678

Abstract: A thin film transistor according to the present invention may include a gate insulating layer; and a lower pattern placed below the gate insulating layer to contact therewith and having an edge with a taper angle of at most about 80°. With this design, dielectric strength of the gate insulating layer can be enhanced. The lower pattern can be a gate electrode layer.

Abstract translation: 根据本发明的薄膜晶体管可以包括栅极绝缘层; 以及放置在栅极绝缘层下方以与其接触并具有至多约80°的锥角的边缘的下部图案。 通过这种设计，可以提高栅极绝缘层的介电强度。 下图案可以是栅极电极层。

公开(公告)号：US20050110090A1

公开(公告)日：2005-05-26

申请号：US10994264

申请日：2004-11-23

Applicant: Jae-Bon Koo ,  Sang-Gul Lee

Inventor： Jae-Bon Koo ,  Sang-Gul Lee

IPC: H01L21/336 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/00 ,  C30B1/00 ,  H01L21/20 ,  H01L21/36 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L29/66757 ,  H01L29/42384 ,  H01L29/78621 ,  H01L29/78627

Abstract: A thin film transistor with a GOLDD structure may include an active layer formed on an insulating substrate including source/drain regions and a channel region. A gate insulating film may be formed on the active layer and a gate electrode may be formed on the gate insulating film. The gate electrode may include a first gate pattern and a second gate pattern formed at sides of the first gate pattern. The source/drain regions may each have an LDD region, and the LDD regions may overlaps-the gate electrode.

Abstract translation: 具有GOLDD结构的薄膜晶体管可以包括形成在包括源极/漏极区域和沟道区域的绝缘基板上的有源层。 可以在有源层上形成栅极绝缘膜，并且可以在栅极绝缘膜上形成栅电极。 栅电极可以包括形成在第一栅极图案的侧面处的第一栅极图案和第二栅极图案。 源极/漏极区域可以各自具有LDD区域，并且LDD区域可能与栅电极重叠。

公开(公告)号：US06562667B1

公开(公告)日：2003-05-13

申请号：US09715188

申请日：2000-11-20

Applicant: Eui-Hoon Hwang ,  Sang-Gul Lee

Inventor： Eui-Hoon Hwang ,  Sang-Gul Lee

IPC: H01L2100

CPC classification number: H01L29/66757 ,  H01L29/78621

Abstract: An object of the present invention is to crystallize and activate the doped amorphous semiconductor layer at the same time. It is also an object to provide the TFT with good electrical connection between the source or drain electrodes and the semiconductor layer. The inventive method of fabricating TFT for a liquid crystal display device, includes forming a buffer layer on a substrate; forming an amorphous semiconductor layer on the whole buffer layer, the semiconductor layer having a channel region and source and drain ohmic contact regions, each positioned at opposing ends of the channel region; doping n+ (or p+) ions on the source and drain ohmic contact regions of the semiconductor layer while covering the channel region with a photoresist; patterning the semiconductor layer to have an island shape, the island shape including the channel region and the source and drain ohmic contact regions; irradiating laser beams on the semiconductor layer having the island shape, thereby crystallizing and activating the semiconductor layer; forming a first insulating layer on the semiconductor layer; forming a gate electrode on the first insulating layer; forming a second insulating layer on the first insulating layer while covering the gate electrode; forming source and drain contact holes penetrating both the first and second insulating layers to the source and drain ohmic contact regions of the semiconductor layer, respectively; and forming the source and drain electrodes on the second insulating layer, while the source and drain electrodes having electrical connection to the source and drain ohmic contact regions of the semiconductor layer.

Abstract translation: 本发明的目的是同时结晶和活化掺杂的非晶半导体层。 本发明的另一个目的是提供TFT在源极或漏极和半导体层之间的良好电连接。本发明制造用于液晶显示器件的TFT的方法包括在衬底上形成缓冲层; 在整个缓冲层上形成非晶半导体层，所述半导体层具有沟道区和源极和漏极欧姆接触区，每个位于沟道区的相对端; 在半导体层的源极和漏极欧姆接触区域上掺杂n +（或p +）离子，同时用光致抗蚀剂覆盖沟道区域; 将半导体层图形化为岛状，该岛状包括沟道区和源极和漏极欧姆接触区; 在具有岛状的半导体层上照射激光束，从而使半导体层结晶并起作用; 在所述半导体层上形成第一绝缘层; 在所述第一绝缘层上形成栅电极; 在覆盖所述栅电极的同时在所述第一绝缘层上形成第二绝缘层; 形成分别将所述第一和第二绝缘层穿过所述半导体层的源极和漏极欧姆接触区域的源极和漏极接触孔; 以及在所述第二绝缘层上形成所述源极和漏极，同时所述源极和漏极与所述半导体层的所述源极和漏极欧姆接触区域电连接。

公开(公告)号：US06458636B1

公开(公告)日：2002-10-01

申请号：US10005124

申请日：2001-12-07

Applicant: Jong-Hoon Yi ,  Sang-Gul Lee ,  Won-Kyu Park

Inventor： Jong-Hoon Yi ,  Sang-Gul Lee ,  Won-Kyu Park

IPC: H01L2100

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L27/1285 ,  H01L29/41733 ,  H01L29/66757 ,  H01L29/78675

Abstract: A method for forming a polycrystalline silicon layer for TFT according to the present invention includes steps of: depositing an amorphous silicon layer and a silicon oxidation layer on a substrate in this order; and implanting semiconductor ions into the amorphous silicon layer and the silicon oxidation layer while heating the substrate, thereby converting the amorphous silicon layer into a polycrystalline silicon layer, and forming an amorphous oxidation layer between the amorphous silicon layer and the silicon oxidation layer.

公开(公告)号：US06395571B1

公开(公告)日：2002-05-28

申请号：US09665119

申请日：2000-09-20

Applicant: Jong Hoon Yi ,  Sang Gul Lee

Inventor： Jong Hoon Yi ,  Sang Gul Lee

IPC: H01L2100

CPC classification number: H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863

Abstract: Fabrication of a polysilicon TFT having a lightly doped drain or offset structure. Fabrication includes forming a semiconductor layer, a gate insulating film, and a gate electrode on a substrate. Then, forming lightly doped impurity regions in the semiconductor layer on both sides of the gate electrode. Next, forming an insulating film having a thickness that gradually becomes thinner away from the gate electrode. Then, forming heavily doped impurity regions in the lightly doped impurity regions in the semiconductor layer on both sides of the gate, resulting in regions with continuously varied impurity concentrations.

Abstract translation: 具有轻掺杂漏极或偏移结构的多晶硅TFT的制造。 制造包括在基板上形成半导体层，栅极绝缘膜和栅电极。 然后，在栅极两侧的半导体层中形成轻掺杂杂质区。 接下来，形成具有从栅电极逐渐变薄的厚度的绝缘膜。 然后，在栅极两侧的半导体层中的轻掺杂杂质区域中形成重掺杂的杂质区域，导致杂质浓度连续变化的区域。

公开(公告)号：US6132840A

公开(公告)日：2000-10-17

申请号：US5666

申请日：1998-01-12

Applicant: Byung Gul Lee

Inventor： Byung Gul Lee

IPC: B29B17/00 ,  C08J11/06 ,  C08J11/04

CPC classification number: C08J11/06 ,  Y02W30/701 ,  Y10T428/24058 ,  Y10T428/24124 ,  Y10T428/24504 ,  Y10T428/24653 ,  Y10T428/24893

Abstract: A fiber resin composite member manufacturing method includes the steps of: selectively distinguishing waste rubber and synthetic resins containing waste tires and waste PET bottles, waste fibers, waste timbers, waste paper, waste plant straws, waste shells from shellfish or clams and so on from industrial waste materials in accordance with their physical chemical features; disintegrating the waste rubber and synthetic resins containing the waste tires and the waste PET bottles in a super low temperature cooling method, disintegrating the waste fibers in an appropriate size by using a scutcher, and distintegrating the other waste materials by means of a general crusher; pouring the disintegrated waste materials into a molding machine in a predetermined composition ratio and melting-molding them in a desired type at a high temperature of about 150 to 300.degree. C. and a high pressure of about 150 to 3,000 ton; and cooling the molded fiber resin composite member at a temperature of about 40 to 70.degree. C. and pressure under about 500 to 800 ton to manufacture a complete product.

Abstract translation: 纤维树脂复合构件的制造方法包括以下步骤：将废旧橡胶和含有废轮胎的合成树脂和废PET瓶，废纤维，废木材，废纸，废植物秸秆，来自贝类或蛤蜊的废物壳等选择性地区分开 工业废料按照其物理化学特性; 在超低温冷却方法中分解含有废轮胎和废PET瓶的废橡胶和合成树脂，通过使用刮刀将废纤维分解成合适的尺寸，并通过一般破碎机将其它废料分解; 将分解的废料以预定的组成比将其倒入成型机中，并在约150〜300℃的高温和约150〜3000吨的高压下以期望的种类进行熔融成型， 并在约40至70℃的温度和约500至800吨的压力下冷却模制的纤维树脂复合材料，以制造完整的产品。

公开(公告)号：US6077730A

公开(公告)日：2000-06-20

申请号：US22415

申请日：1998-02-12

Applicant: Sang-Gul Lee ,  Ju-Cheon Yeo ,  Yong-Min Ha

Inventor： Sang-Gul Lee ,  Ju-Cheon Yeo ,  Yong-Min Ha

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/84

CPC classification number: H01L27/127 ,  H01L29/78621

Abstract: A method is provided for fabricating a thin film transistor on a substrate. The method includes the steps of forming an active layer having a channel region on the substrate, forming an impurity-blocking mask covering the channel region and portions of the active layer outside the channel region adjacent the channel region, and doping impurities of a first conductivity type at a high density into portions of the active layer uncovered by the impurity-blocking mask to form impurity-doped regions in the active layer. The method further includes the steps of removing the impurity-blocking mask and thereafter performing a plasma treatment on the resultant structure using a plasma gas containing impurities of the first conductivity type to form LDD regions in the active layer between the channel region and the impurity-doped regions.

Abstract translation: 提供了一种在衬底上制造薄膜晶体管的方法。 该方法包括以下步骤：在衬底上形成具有沟道区的有源层，形成覆盖沟道区的杂质阻挡掩模和与沟道区相邻的沟道区之外的有源层的部分，以及掺杂第一导电性的杂质 以高密度键入由杂质阻挡掩模未覆盖的有源层的部分，以在有源层中形成杂质掺杂区域。 该方法还包括以下步骤：去除杂质阻挡掩模，然后使用含有第一导电类型的杂质的等离子气体对所得结构进行等离子体处理，以在沟道区和杂质阻挡掩模之间的有源层中形成LDD区， 掺杂区域。

公开(公告)号：US5835172A

公开(公告)日：1998-11-10

申请号：US874659

申请日：1997-06-13

Applicant: Ju-Cheon Yeo ,  Sang-Gul Lee

Inventor： Ju-Cheon Yeo ,  Sang-Gul Lee

IPC: G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78645

Abstract: A thin-film transistor liquid crystal display includes a substrate, an active layer on the substrate, having first and second impurity regions and first, second, and third non-impurity regions, gate insulating layer on the active layer, first and second electric field control layers on the second and third non-impurity regions, respectively, first and second subsidiary gate electrodes on the first and second electric field control layers, respectively, and a main gate electrode on the gate insulating layer, the main gate electrode contacting the first and second subsidiary gate electrodes and the first and second electric field control layers, respectively.

Abstract translation: 薄膜晶体管液晶显示器包括基板，基板上的有源层，具有第一和第二杂质区域以及第一，第二和第三非杂质区域，有源层上的栅极绝缘层，第一和第二电场 第二和第三非杂质区域上的控制层分别分别在第一和第二电场控制层上的第一和第二辅助栅电极以及栅极绝缘层上的主栅电极，主栅电极接触第一 和第二副栅极电极以及第一和第二电场控制层。