公开(公告)号：US07973310B2

公开(公告)日：2011-07-05

申请号：US12501100

申请日：2009-07-10

申请人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

发明人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

IPC分类号： H01L23/58

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.

摘要翻译： 提供半导体封装结构及其制造方法。 半导体封装结构包括衬底单元和第一芯片堆叠结构。 衬底单元包括具有测试焊盘的电路结构。 第一芯片堆叠结构包括芯片，并且每个芯片具有多个通硅插头。 两个相邻芯片的贯穿硅插头电连接并且进一步电连接到用于电测试的衬底单元的测试焊盘。 由本发明提供的另一半导体封装结构包括第一半导体芯片和第二半导体芯片。 每个半导体芯片具有用于电测试的测试焊盘和连接到测试焊盘的多个穿硅插头。 第二半导体芯片安装在第一半导体芯片上，并且两个半导体芯片的贯穿硅插头的一部分彼此电连接。

公开(公告)号：US20100007001A1

公开(公告)日：2010-01-14

申请号：US12501100

申请日：2009-07-10

申请人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

发明人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

IPC分类号： H01L23/52 ,  H01L23/538 ,  H01L21/98 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.

摘要翻译： 提供半导体封装结构及其制造方法。 半导体封装结构包括衬底单元和第一芯片堆叠结构。 衬底单元包括具有测试焊盘的电路结构。 第一芯片堆叠结构包括芯片，并且每个芯片具有多个通硅插头。 两个相邻芯片的贯穿硅插头电连接并且进一步电连接到用于电测试的衬底单元的测试焊盘。 由本发明提供的另一半导体封装结构包括第一半导体芯片和第二半导体芯片。 每个半导体芯片具有用于电测试的测试焊盘和连接到测试焊盘的多个穿硅插头。 第二半导体芯片安装在第一半导体芯片上，并且两个半导体芯片的贯穿硅插头的一部分彼此电连接。

公开(公告)号：US20090283905A1

公开(公告)日：2009-11-19

申请号：US12262766

申请日：2008-10-31

申请人： Hsiang-Ming HUANG ,  An-Hong Liu ,  Yi-Chang Lee ,  Hao-Yin Tsai ,  Shu-Ching Ho

发明人： Hsiang-Ming HUANG ,  An-Hong Liu ,  Yi-Chang Lee ,  Hao-Yin Tsai ,  Shu-Ching Ho

IPC分类号： H01L23/488

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014

摘要： A conductive structure of a chip is provided. The conductive structure comprises a ground layer, a dielectric layer, a redistribution layer, an under bump metal and a solder bump. The ground layer electrically connects to the ground pad of the chip, while the dielectric layer overlays the ground layer. Thus, the conductive layer can result in impedance matching, and the packaged chip is adapted to transmit a high frequency signal.

摘要翻译： 提供了芯片的导电结构。 导电结构包括接地层，电介质层，再分配层，凸块下金属和焊料凸块。 接地层电连接到芯片的接地焊盘，而电介质层覆盖接地层。 因此，导电层可以导致阻抗匹配，并且封装的芯片适于传输高频信号。

公开(公告)号：US20090236741A1

公开(公告)日：2009-09-24

申请号：US12262682

申请日：2008-10-31

申请人： Hsiang-Ming HUANG ,  An-Hong Liu ,  Yi-Chang Lee ,  Hao-Yin Tsai ,  Shu-Ching Ho

发明人： Hsiang-Ming HUANG ,  An-Hong Liu ,  Yi-Chang Lee ,  Hao-Yin Tsai ,  Shu-Ching Ho

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

摘要： A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the photomask can be economized and the cost of manufacturing can be reduced.

摘要翻译： 提供了芯片的导电结构和制造导电结构的方法。 通过进行化学镀处理，在再分布层（RDL）上形成凹凸金属（UBM）。 随后，焊料凸块形成在凸块下金属上用于电连接。 因此，可以节省光掩模并且可以降低制造成本。