公开(公告)号：US20100007001A1

公开(公告)日：2010-01-14

申请号：US12501100

申请日：2009-07-10

申请人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

发明人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

IPC分类号： H01L23/52 ,  H01L23/538 ,  H01L21/98 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.

摘要翻译： 提供半导体封装结构及其制造方法。 半导体封装结构包括衬底单元和第一芯片堆叠结构。 衬底单元包括具有测试焊盘的电路结构。 第一芯片堆叠结构包括芯片，并且每个芯片具有多个通硅插头。 两个相邻芯片的贯穿硅插头电连接并且进一步电连接到用于电测试的衬底单元的测试焊盘。 由本发明提供的另一半导体封装结构包括第一半导体芯片和第二半导体芯片。 每个半导体芯片具有用于电测试的测试焊盘和连接到测试焊盘的多个穿硅插头。 第二半导体芯片安装在第一半导体芯片上，并且两个半导体芯片的贯穿硅插头的一部分彼此电连接。

公开(公告)号：US20090283905A1

公开(公告)日：2009-11-19

申请号：US12262766

申请日：2008-10-31

申请人： Hsiang-Ming HUANG ,  An-Hong Liu ,  Yi-Chang Lee ,  Hao-Yin Tsai ,  Shu-Ching Ho

发明人： Hsiang-Ming HUANG ,  An-Hong Liu ,  Yi-Chang Lee ,  Hao-Yin Tsai ,  Shu-Ching Ho

IPC分类号： H01L23/488

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014

摘要： A conductive structure of a chip is provided. The conductive structure comprises a ground layer, a dielectric layer, a redistribution layer, an under bump metal and a solder bump. The ground layer electrically connects to the ground pad of the chip, while the dielectric layer overlays the ground layer. Thus, the conductive layer can result in impedance matching, and the packaged chip is adapted to transmit a high frequency signal.

摘要翻译： 提供了芯片的导电结构。 导电结构包括接地层，电介质层，再分配层，凸块下金属和焊料凸块。 接地层电连接到芯片的接地焊盘，而电介质层覆盖接地层。 因此，导电层可以导致阻抗匹配，并且封装的芯片适于传输高频信号。

公开(公告)号：US07973310B2

公开(公告)日：2011-07-05

申请号：US12501100

申请日：2009-07-10

申请人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

发明人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

IPC分类号： H01L23/58

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.

摘要翻译： 提供半导体封装结构及其制造方法。 半导体封装结构包括衬底单元和第一芯片堆叠结构。 衬底单元包括具有测试焊盘的电路结构。 第一芯片堆叠结构包括芯片，并且每个芯片具有多个通硅插头。 两个相邻芯片的贯穿硅插头电连接并且进一步电连接到用于电测试的衬底单元的测试焊盘。 由本发明提供的另一半导体封装结构包括第一半导体芯片和第二半导体芯片。 每个半导体芯片具有用于电测试的测试焊盘和连接到测试焊盘的多个穿硅插头。 第二半导体芯片安装在第一半导体芯片上，并且两个半导体芯片的贯穿硅插头的一部分彼此电连接。

公开(公告)号：US20090236741A1

公开(公告)日：2009-09-24

申请号：US12262682

申请日：2008-10-31

申请人： Hsiang-Ming HUANG ,  An-Hong Liu ,  Yi-Chang Lee ,  Hao-Yin Tsai ,  Shu-Ching Ho

发明人： Hsiang-Ming HUANG ,  An-Hong Liu ,  Yi-Chang Lee ,  Hao-Yin Tsai ,  Shu-Ching Ho

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

摘要： A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the photomask can be economized and the cost of manufacturing can be reduced.

摘要翻译： 提供了芯片的导电结构和制造导电结构的方法。 通过进行化学镀处理，在再分布层（RDL）上形成凹凸金属（UBM）。 随后，焊料凸块形成在凸块下金属上用于电连接。 因此，可以节省光掩模并且可以降低制造成本。

公开(公告)号：US20080124828A1

公开(公告)日：2008-05-29

申请号：US11601753

申请日：2006-11-20

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Shu-Ching Ho ,  Yi-Chang Lee ,  Yeong-Jyh Lin

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Shu-Ching Ho ,  Yi-Chang Lee ,  Yeong-Jyh Lin

IPC分类号： H01L21/56

CPC分类号： G01R1/06744 ,  G01R3/00

摘要： MEMS processes for fabrication of a MEMS alloy probe are revealed. Multiple layers of the MEMS alloy probe are formed on the substrate in sequences as a first surface layer, a first conductive layer, a core layer, a second conductive layer, and a second surface layer where the width of the first conductive layer is smaller than the one of first surface layer so that all the exposed edges of the first surface layer are not covered by the first conductive layer. The second surface layer is extended from the sidewalls of the core layer to the exposed edges of the first surface layer to encapsulate the core layer, the first conductive layer, and the second conductive layer. The MEMS alloy probe fabricated by the MEMS processes can eliminate the issue of oxidation.

摘要翻译： 揭示了用于制造MEMS合金探针的MEMS工艺。 多层MEMS合金探针以顺序形成在基板上，作为第一表面层，第一导电层，芯层，第二导电层和第二表面层，其中第一导电层的宽度小于 第一表面层中的一个，使得第一表面层的所有暴露边缘都不被第一导电层覆盖。 第二表面层从芯层的侧壁延伸到第一表面层的暴露边缘，以封装芯层，第一导电层和第二导电层。 通过MEMS工艺制造的MEMS合金探针可以消除氧化问题。

公开(公告)号：US20110291267A1

公开(公告)日：2011-12-01

申请号：US12856754

申请日：2010-08-16

申请人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yi-Chang Lee

发明人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yi-Chang Lee

IPC分类号： H01L23/498

CPC分类号： H01L23/481 ,  H01L21/563 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface. Hence, the reliability of multi-chip stack package structure can be enhanced with the application of these soft metal caps.

摘要翻译： 半导体晶片结构包括第一表面和与第一表面相对的第二表面，形成在第一表面上的多个芯片区域，多个通孔形成在多个芯片区域中的每一个中，所述多个芯片区域连接第一表面和 第二表面和形成在每个贯通硅孔中的贯通硅通孔（TSV）电极结构。 每个贯通硅通孔电极结构包括形成在通孔的内壁上的电介质层，形成在电介质层的内壁上并在其中限定空位的阻挡层，填充到空位中的填充金属层 ，所述填充金属层的第一端低于形成凹部的第一表面;以及连接到所述填充金属层的第一端并覆盖所述填充金属层的第一端的软金属帽，其中所述软金属帽的一部分形成在所述凹部 并且软金属帽从第一表面突出。 因此，通过应用这些软金属盖，可以提高多芯片堆叠封装结构的可靠性。

公开(公告)号：US07372286B2

公开(公告)日：2008-05-13

申请号：US11322408

申请日：2006-01-03

申请人： Yi-Chang Lee ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yao-Jung Lee ,  Yeong-Her Wang

发明人： Yi-Chang Lee ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yao-Jung Lee ,  Yeong-Her Wang

IPC分类号： G01R1/073

CPC分类号： G01R1/07378

摘要： A modular probe card comprises a printed circuit board, an interposer, and a probe head where the printed circuit board has a plurality of first contact pads, the probe head has a plurality of second contact pads. The interposer is disposed between the printed circuit board and the probe head where the interposer includes a substrate and a plurality of pogo pins. The substrate has a first surface, a second surface, and a plurality of through holes penetrating from the first surface to the second surface. The pogo pins are secured in the through holes of the substrate. Each of the pogo pins has a first contact point, a second contact point, and a spring therebetween, whereby the first contact points are elastically extruded from the first surface to contact the first contact pad, and the second contact points are elastically extruded from the second surface to contact the second contact pad, so as to overcome the poor electrical connections between the printed circuit board and the probe head through the interposer due to poor coplanarity of the first contact pads of the printed circuit board.

摘要翻译： 模块化探针卡包括印刷电路板，插入件和探针头，其中印刷电路板具有多个第一接触焊盘，探头具有多个第二接触焊盘。 插入器设置在印刷电路板和探针头之间，其中插入器包括基板和多个弹簧销。 基板具有从第一表面到第二表面的第一表面，第二表面和多个通孔。 弹簧销固定在基板的通孔中。 每个弹簧销具有第一接触点，第二接触点和它们之间的弹簧，由此第一接触点从第一表面弹性挤出以接触第一接触垫，并且第二接触点从 第二表面接触第二接触焊盘，以便克服印刷电路板和探针头之间通过插入器的不良电连接，因为印刷电路板的第一接触焊盘的共面性差。

公开(公告)号：US20070235871A1

公开(公告)日：2007-10-11

申请号：US11400182

申请日：2006-04-10

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee ,  Wu-Chang Tu ,  Chun-Hung Lin ,  Shih Chiu

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee ,  Wu-Chang Tu ,  Chun-Hung Lin ,  Shih Chiu

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/13 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/9202 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.

摘要翻译： 高频IC封装主要包括衬底，凸起芯片和多个导电填料，其中衬底具有从顶表面到底表面穿透的多个凸起孔。 芯片的有源表面以分别插入到凸块孔中的方式附接到基板的顶表面。 导电填料形成在凸起孔中，以将凸块电连接到基板的电路层。 高频IC封装具有更短的电路径和更薄的封装厚度。

公开(公告)号：US20070080452A1

公开(公告)日：2007-04-12

申请号：US11514329

申请日：2006-09-01

申请人： Chen-Ya- Chi ,  Chun-Ying Lin ,  An-Hong Liu ,  Yi-Chang Lee ,  Hsiang-Ming Huang

发明人： Chen-Ya- Chi ,  Chun-Ying Lin ,  An-Hong Liu ,  Yi-Chang Lee ,  Hsiang-Ming Huang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10977 ,  H05K2203/049 ,  H05K2203/0597 ,  H01L2924/00 ,  H01L2224/05599

摘要： A bump structure mainly includes a metal core, a buffer encapsulant, and a metal cap where the metal core is a stud bump formed by wire bonding. The buffer encapsulant encapsulates the metal core. A metal cap is formed on the top surface of the buffer encapsulant and is electrically connected to the metal core. Therefore, the bump structure possesses excellent resistance of thermal stress to reduce or even eliminate metal fatigue in the bump without causing electrical shorts in the package.

摘要翻译： 凸块结构主要包括金属芯，缓冲密封剂和金属盖，其中金属芯是通过引线键合形成的柱形凸块。 缓冲密封剂封装金属芯。 金属盖形成在缓冲密封剂的顶表面上并与金属芯电连接。 因此，凸块结构具有优异的热应力阻力，以减少或甚至消除凸块中的金属疲劳，而不会导致封装中的电短路。

公开(公告)号：US20070069749A1

公开(公告)日：2007-03-29

申请号：US11605442

申请日：2006-11-29

申请人： Yi-Chang Lee ,  An-Hong Liu ,  Yeong-Her Wang ,  Yeong-Ching Chao ,  Hsiang-Ming Huang

发明人： Yi-Chang Lee ,  An-Hong Liu ,  Yeong-Her Wang ,  Yeong-Ching Chao ,  Hsiang-Ming Huang

IPC分类号： G01R31/02

CPC分类号： G01R3/00 ,  G01R1/06716 ,  G01R1/06744 ,  G01R1/07342 ,  H01R13/2414 ,  H01R43/007 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.

摘要翻译： 公开了一排形成多个弹性探针的方法。 首先，提供基板，然后在基板上形成成形层，以便平行地提供两个平坦表面。 在基板上和形成层上形成光致抗蚀剂层。 然后，对光致抗蚀剂层进行图案化以形成与两个平坦表面之间的界面交叉的多个槽，其中在槽中形成有多个弹性探针。 在一个实施例中，界面是成形层的边缘斜率，使得每个弹性探针具有至少一个弹性弯曲部分。 在芯片探测期间，由于过驱动导致的弹性探针的移动方向垂直于接合焊盘的布置方向，使得弹性探头适用于探测具有高密度和细间距接合焊盘的芯片。