公开(公告)号：US20130069228A1

公开(公告)日：2013-03-21

申请号：US13559087

申请日：2012-07-26

申请人： An-Hong LIU ,  Hung-Hsin Liu ,  Jar-Dar Yang ,  Chi-Chia Huang ,  Yi-Chang Lee ,  Hsiang-Ming Huang

发明人： An-Hong LIU ,  Hung-Hsin Liu ,  Jar-Dar Yang ,  Chi-Chia Huang ,  Yi-Chang Lee ,  Hsiang-Ming Huang

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/16 ,  H01L23/49894 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/13021 ,  H01L2224/14136 ,  H01L2224/73203 ,  H01L2224/81139 ,  H01L2224/92125

摘要： A flip-chip package structure comprising a substrate, a chip, a bump structure and a solder resist is provided. The substrate has a circuit layer disposed on the surface thereof. The chip comprises a central region and two edge regions disposed on the two sides of the central region. The bump structure is disposed on the central region of the chip and faces the substrate. The solder resist is disposed on the substrate to partially cover the circuit layer. The chip is electrically connected to the substrate by the bump structure, and the solder resist is adapted to come into contact with the two edge regions of the chip to support the chip with the bump structure when the chip is disposed on the substrate.

摘要翻译： 提供了包括衬底，芯片，凸块结构和阻焊剂的倒装芯片封装结构。 基板具有设置在其表面上的电路层。 芯片包括设置在中心区域两侧的中心区域和两个边缘区域。 凸块结构设置在芯片的中心区域并面向衬底。 阻焊剂设置在基板上以部分地覆盖电路层。 芯片通过凸块结构电连接到衬底，并且当芯片设置在衬底上时，阻焊层适于与芯片的两个边缘区域接触以支撑具有凸块结构的芯片。

公开(公告)号：US20130049787A1

公开(公告)日：2013-02-28

申请号：US13445067

申请日：2012-04-12

申请人： Chi-Ming YI ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yi-Chang Lee

发明人： Chi-Ming YI ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yi-Chang Lee

IPC分类号： G01R31/00

CPC分类号： H01L22/14 ,  G01R31/2853 ,  G01R31/318513 ,  H01L22/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/00

摘要： The present invention provides a method of testing a stacked semiconductor device structure. This method includes the following steps: providing a testing board having a plurality of testing points and a probe card; providing a substrate which is disposed on the testing board; providing a plurality of semiconductor devices; mounting and electrically connecting a first one of the semiconductor devices onto the substrate; mounting and electrically connecting a second one of the semiconductor devices onto the first one of the semiconductor devices; keeping the probe card in contact with the second one of the semiconductor devices for electrical testing; and repeating the steps of mounting and testing of the semiconductor devices until all of the semiconductor devices are tested. This method can ensure the integrity of electrical interconnections between the semiconductor devices of the stacked structure.

摘要翻译： 本发明提供一种测试堆叠半导体器件结构的方法。 该方法包括以下步骤：提供具有多个测试点和探针卡的测试板; 提供设置在测试板上的基板; 提供多个半导体器件; 将第一个半导体器件安装并电连接到衬底上; 将第二个半导体器件安装并电连接到第一个半导体器件上; 保持探针卡与第二个半导体器件接触进行电气测试; 并重复安装和测试半导体器件的步骤，直到所有半导体器件被测试。 该方法可以确保层叠结构的半导体器件之间的电互连的完整性。

公开(公告)号：US20120255913A1

公开(公告)日：2012-10-11

申请号：US13159361

申请日：2011-06-13

申请人： Mean-Jue Tung ,  Yu-Ting Huang ,  Li-Kou Chen ,  Yi-Shan Lin ,  Hsiang-Ming Huang ,  Shinn-Zong Lin ,  Woei-Cherng Shyu ,  Hsiao-Jung Wang

发明人： Mean-Jue Tung ,  Yu-Ting Huang ,  Li-Kou Chen ,  Yi-Shan Lin ,  Hsiang-Ming Huang ,  Shinn-Zong Lin ,  Woei-Cherng Shyu ,  Hsiao-Jung Wang

IPC分类号： B03C1/00

CPC分类号： B03C1/288 ,  B03C1/0332 ,  B03C2201/18 ,  B03C2201/26 ,  G01N33/0098 ,  Y10T436/25 ,  Y10T436/25375 ,  Y10T436/255

摘要： A magnetic separation unit is provided, including a first member made of non-magnetic materials comprising a trench extending within the first member and a second member made of magnetic materials including a protrusion portion protruding over a surface of the second member, wherein the first member connects the second member such that the trench functions as a fluid channel formed between the first and second members, and the protrusion portion of the second member is contained by the trench of the first member.

摘要翻译： 提供一种磁分离单元，包括由非磁性材料制成的第一构件，该第一构件包括在第一构件内延伸的沟槽和由包括突出部分在第二构件的表面上突出的磁性材料制成的第二构件，其中第一构件 连接第二构件，使得沟槽用作形成在第一和第二构件之间的流体通道，并且第二构件的突出部分被第一构件的沟槽包围。

公开(公告)号：US08269351B2

公开(公告)日：2012-09-18

申请号：US13004936

申请日：2011-01-12

申请人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Jar-Dar Yang ,  Yi-Chang Lee

发明人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Jar-Dar Yang ,  Yi-Chang Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

公开(公告)号：US20110309496A1

公开(公告)日：2011-12-22

申请号：US13004946

申请日：2011-01-12

申请人： David Wei WANG ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Jar-Dar Yang ,  Yi-Chang Lee

发明人： David Wei WANG ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Jar-Dar Yang ,  Yi-Chang Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

公开(公告)号：US20110309495A1

公开(公告)日：2011-12-22

申请号：US13004936

申请日：2011-01-12

申请人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Jar-Dar Yang ,  Yi-Chang Lee

发明人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Jar-Dar Yang ,  Yi-Chang Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

摘要翻译： 多芯片堆叠封装结构包括：衬底，其具有限定在其上表面上的芯片放置区域和布置在芯片放置区域外部的多个触点; 第一芯片设置在具有后表面的芯片布置区域中，多个第一焊盘设置在有源表面上，并且多个第一凸块各自形成在第一焊盘之一上; 多个金属线将第一凸块连接到触点; 具有多个第二焊盘的第二芯片设置在所述有源表面上，并且多个第二凸块各自形成在所述第二焊盘之一上，所述第二芯片安装到所述第一芯片，其有源表面面向所述第二焊盘的有效表面 第一芯片，其中所述第二凸块分别对应地连接所述金属线和所述第一凸块。

公开(公告)号：US07973310B2

公开(公告)日：2011-07-05

申请号：US12501100

申请日：2009-07-10

申请人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

发明人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

IPC分类号： H01L23/58

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.

摘要翻译： 提供半导体封装结构及其制造方法。 半导体封装结构包括衬底单元和第一芯片堆叠结构。 衬底单元包括具有测试焊盘的电路结构。 第一芯片堆叠结构包括芯片，并且每个芯片具有多个通硅插头。 两个相邻芯片的贯穿硅插头电连接并且进一步电连接到用于电测试的衬底单元的测试焊盘。 由本发明提供的另一半导体封装结构包括第一半导体芯片和第二半导体芯片。 每个半导体芯片具有用于电测试的测试焊盘和连接到测试焊盘的多个穿硅插头。 第二半导体芯片安装在第一半导体芯片上，并且两个半导体芯片的贯穿硅插头的一部分彼此电连接。

公开(公告)号：US07368809B2

公开(公告)日：2008-05-06

申请号：US11228234

申请日：2005-09-19

申请人： Hsiang-Ming Huang ,  Yeong-Ching Chao ,  Yi-Chang Lee ,  An-Hong Liu

发明人： Hsiang-Ming Huang ,  Yeong-Ching Chao ,  Yi-Chang Lee ,  An-Hong Liu

IPC分类号： H01L23/02 ,  H01L21/44

CPC分类号： H01L21/4853 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/85181 ,  H01L2224/92147 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0401

摘要： A pillar grid array package (PGA) includes a substrate, a chip disposed on top of the substrate, and a plurality of stud bumps disposed on bottom of the substrate. The stud bumps are formed in an array and each has a flattened top to electrically connect to a printed circuit board, PCB, by an anisotropic conductive paste to achieve a thin package and to avoid substrate warpage problems of a ball grid array (BGA) during high-temperature reflow processes.

摘要翻译： 支柱阵列封装（PGA）包括衬底，设置在衬底顶部的芯片和设置在衬底底部的多个柱形凸块。 柱形凸起形成为阵列，并且每个具有平坦的顶部，以通过各向异性导电膏电连接到印刷电路板PCB，以实现薄的封装并避免球栅阵列（BGA）的基板翘曲问题 高温回流工艺。

公开(公告)号：US20070262439A1

公开(公告)日：2007-11-15

申请号：US11583951

申请日：2006-10-20

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L23/3135 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49572 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.

摘要翻译： 一种用于增强嵌入式凸块的结合性的IC封装，主要包括具有多个凸块容纳孔，凸起芯片，密封剂和多个外部端子的基板。 基板还分别在凸块容纳孔的一​​端具有多个内垫。 内部焊盘可以是啮合的，或者在其上设置焊接层以改善凸块连接。 芯片被附接到基板上，凸块对准并嵌入在相应的凸起容纳孔中。 密封剂至少形成在基底的下表面上以封装网眼或焊接层。 通过悬挂的网格或/和焊接层，可以在较低的温度下容易地接合凸块，以简化具有更短导电路径和更薄的封装形状的制造工艺，而无需扫线。

公开(公告)号：US20070085554A1

公开(公告)日：2007-04-19

申请号：US11249464

申请日：2005-10-14

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yi-Chang Lee ,  Yao-Jung Lee ,  Yeong-Her Wang

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yi-Chang Lee ,  Yao-Jung Lee ,  Yeong-Her Wang

IPC分类号： G01R31/02

CPC分类号： G01R31/2886 ,  G01R1/07364

摘要： A replaceable modular probe head is composed of a plurality of in-parallel probing modules. Each probing module has a plurality of in-series probing regions. In the present embodiment, each probing module has mechanical connection parts on its both ends to attach to a printed circuit board (PCB) to be a multi-DUT probe card. Therefore, the probing module can be replaced individually when probes are damaged or worn without replacing the whole probe head to reduce the fabrication cost of a multi-DUT probe head.

摘要翻译： 可替换的模块化探头由多个并联探测模块组成。 每个探测模块具有多个串联探测区域。 在本实施例中，每个探测模块的两端具有机械连接部分，以连接到作为多DUT探针卡的印刷电路板（PCB）。 因此，当探头损坏或磨损时，可以单独更换探测模块，而无需更换整个探头，从而降低多DUT探头的制造成本。