公开(公告)号：US08550345B2

公开(公告)日：2013-10-08

申请号：US12120909

申请日：2008-05-15

申请人： Cheng-Fang Huang ,  Pin-Hsun Huang ,  Chih-Hsiang Wang ,  Wen-Cheng Hsu ,  Yi-fang cho ,  An-Hong Liu ,  Yi-Chang Lee

发明人： Cheng-Fang Huang ,  Pin-Hsun Huang ,  Chih-Hsiang Wang ,  Wen-Cheng Hsu ,  Yi-fang cho ,  An-Hong Liu ,  Yi-Chang Lee

IPC分类号： G06F19/00

CPC分类号： G06Q10/08

摘要： This invention provides an RFID real-time information system accommodated to a semiconductor supply chain for exchanging real-time information. The RFID real-time information system is characterized by comprising an RFID middleware module for generating a stock and logistic information corresponding to a plurality of carriers and wafers from a tag information; a manufacturing information module for storing an object information corresponding to the plurality of wafers; a real-time information module for integrating the RFID middleware module with the manufacturing information module to generate real-time information corresponding to the plurality of wafers and carriers; and a business-to-business (B2B) e-commerce module comprising a plurality of B2B servers respectively disposed in vendors in the semiconductor supply chain for connecting and exchanging the real-time information through a standard protocol of e-commerce.

摘要翻译： 本发明提供一种适用于半导体供应链的RFID实时信息系统，用于交换实时信息。 RFID实时信息系统的特征在于包括：RFID中间件模块，用于从标签信息生成对应于多个载体和晶片的库存和物流信息; 制造信息模块，用于存储对应于所述多个晶片的对象信息; 实时信息模块，用于将RFID中间件模块与制造信息模块集成，以生成与多个晶片和载体对应的实时信息; 以及分别设置在半导体供应链的供应商中的多个B2B服务器的企业对企业（B2B）电子商务模块，用于通过电子商务的标准协议来连接和交换实时信息。

公开(公告)号：US08264068B2

公开(公告)日：2012-09-11

申请号：US13004960

申请日：2011-01-12

申请人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Jar-Dar Yang ,  Yi-Chang Lee

发明人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Jar-Dar Yang ,  Yi-Chang Lee

IPC分类号： H01L29/40

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

公开(公告)号：US07642639B2

公开(公告)日：2010-01-05

申请号：US11583951

申请日：2006-10-20

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee

IPC分类号： H01L23/04 ,  H01L23/48

CPC分类号： H01L23/3135 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49572 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.

摘要翻译： 一种用于增强嵌入式凸块的结合性的IC封装，主要包括具有多个凸块容纳孔，凸起芯片，密封剂和多个外部端子的基板。 基板还分别在凸块容纳孔的一​​端具有多个内垫。 内部焊盘可以是啮合的，或者在其上设置焊接层以改善凸块连接。 芯片被附接到基板上，凸块对准并嵌入在相应的凸起容纳孔中。 密封剂至少形成在基底的下表面上以封装网眼或焊接层。 通过悬挂的网格或/和焊接层，可以在较低的温度下容易地接合凸块，以简化具有更短导电路径和更薄的封装形状的制造工艺，而无需扫线。

公开(公告)号：US20090236741A1

公开(公告)日：2009-09-24

申请号：US12262682

申请日：2008-10-31

申请人： Hsiang-Ming HUANG ,  An-Hong Liu ,  Yi-Chang Lee ,  Hao-Yin Tsai ,  Shu-Ching Ho

发明人： Hsiang-Ming HUANG ,  An-Hong Liu ,  Yi-Chang Lee ,  Hao-Yin Tsai ,  Shu-Ching Ho

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

摘要： A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the photomask can be economized and the cost of manufacturing can be reduced.

摘要翻译： 提供了芯片的导电结构和制造导电结构的方法。 通过进行化学镀处理，在再分布层（RDL）上形成凹凸金属（UBM）。 随后，焊料凸块形成在凸块下金属上用于电连接。 因此，可以节省光掩模并且可以降低制造成本。

公开(公告)号：US07554197B2

公开(公告)日：2009-06-30

申请号：US11400182

申请日：2006-04-10

申请人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee ,  Wu-Chang Tu ,  Chun-Hung Lin ,  Shih Feng Chiu

发明人： Hsiang-Ming Huang ,  An-Hong Liu ,  Yeong-Jyh Lin ,  Yi-Chang Lee ,  Wu-Chang Tu ,  Chun-Hung Lin ,  Shih Feng Chiu

IPC分类号： H01L23/48 ,  H01L23/28 ,  H01L23/29

CPC分类号： H01L24/10 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/13 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/9202 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.

摘要翻译： 高频IC封装主要包括衬底，凸起芯片和多个导电填料，其中衬底具有从顶表面到底表面穿透的多个凸起孔。 芯片的有源表面以分别插入到凸块孔中的方式附接到基板的顶表面。 导电填料形成在凸起孔中，以将凸块电连接到基板的电路层。 高频IC封装具有更短的电路径和更薄的封装厚度。

公开(公告)号：US07443276B2

公开(公告)日：2008-10-28

申请号：US11215516

申请日：2005-08-30

申请人： Chun-Hsiao Wang ,  Yi-Chang Lee

发明人： Chun-Hsiao Wang ,  Yi-Chang Lee

IPC分类号： H01F27/28

CPC分类号： H02M3/33523

摘要： A galvanic isolated digital output circuit of a digital system is provided herein, which utilizes an electromagnetic coupling device for galvanically isolating the system side and the output side of the digital output circuit. The digital output circuit contains a system-side driving circuit, an electromagnetic coupling device, and an output-side control circuit. The electromagnetic coupling device contains at least a system-side electromagnetic coupling element, a first output-side electromagnetic coupling element, and a second output-side electromagnetic coupling element. The system-side driving circuit is connected to the system-side electromagnetic coupling element, and takes the ON/OFF digital control signals from the digital system as input to turn on and off its driving to the system-side electromagnetic coupling element. The electromagnetic coupling device converts and transmits the electrical energy from the system side to the output side and thereby provides the working energy to and required by the output control circuit connected to the first output-side electromagnetic coupling element. The second output-side electromagnetic coupling element forms a feedback circuit, through which the electrical status at the output side is fed back to the system side via the electromagnetic coupling device.

摘要翻译： 本文提供了一种数字系统的电隔离数字输出电路，其利用电磁耦合装置来电隔离数字输出电路的系统侧和输出侧。 数字输出电路包括系统侧驱动电路，电磁耦合装置和输出侧控制电路。 电磁耦合装置至少包括系统侧电磁耦合元件，第一输出侧电磁耦合元件和第二输出侧电磁耦合元件。 系统侧驱动电路连接到系统侧电磁耦合元件，并将来自数字系统的ON / OFF数字控制信号作为输入，将其驱动接通和断开到系统侧电磁耦合元件。 电磁耦合装置将电能从系统侧转换并传输到输出侧，从而提供与连接到第一输出侧电磁耦合元件的输出控制电路所需的工作能量。 第二输出侧电磁耦合元件形成反馈电路，通过该反馈电路，输出侧的电气状态通过电磁耦合装置反馈到系统侧。

公开(公告)号：US07316065B2

公开(公告)日：2008-01-08

申请号：US11364330

申请日：2006-03-01

申请人： Yi-Chang Lee ,  An-Hong Liu ,  Yeong-Her Wang ,  Yeong-Ching Chao ,  Hsiang-Ming Huang

发明人： Yi-Chang Lee ,  An-Hong Liu ,  Yeong-Her Wang ,  Yeong-Ching Chao ,  Hsiang-Ming Huang

IPC分类号： G01R3/00

CPC分类号： G01R3/00 ,  G01R1/06716 ,  G01R1/06744 ,  G01R1/07342 ,  H01R13/2414 ,  H01R43/007 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.

摘要翻译： 公开了一排形成多个弹性探针的方法。 首先，提供基板，然后在基板上形成成形层，以便平行地提供两个平坦表面。 在基板上和形成层上形成光致抗蚀剂层。 然后，对光致抗蚀剂层进行图案化以形成与两个平坦表面之间的界面交叉的多个槽，其中在槽中形成有多个弹性探针。 在一个实施例中，界面是成形层的边缘斜率，使得每个弹性探针具有至少一个弹性弯曲部分。 在芯片探测期间，由于过驱动导致的弹性探针的移动方向垂直于接合焊盘的布置方向，使得弹性探头适用于探测具有高密度和细间距接合焊盘的芯片。

公开(公告)号：US20070152689A1

公开(公告)日：2007-07-05

申请号：US11322408

申请日：2006-01-03

申请人： Yi-Chang Lee ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yao-Jung Lee ,  Yeong-Her Wang

发明人： Yi-Chang Lee ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yao-Jung Lee ,  Yeong-Her Wang

IPC分类号： G01R31/02

CPC分类号： G01R1/07378

摘要： A modular probe card comprises a printed circuit board, an interposer, and a probe head where the printed circuit board has a plurality of first contact pads, the probe head has a plurality of second contact pads. The interposer is disposed between the printed circuit board and the probe head where the interposer includes a substrate and a plurality of pogo pins. The substrate has a first surface, a second surface, and a plurality of through holes penetrating from the first surface to the second surface. The pogo pins are secured in the through holes of the substrate. Each of the pogo pins has a first contact point, a second contact point, and a spring therebetween, whereby the first contact points are elastically extruded from the first surface to contact the first contact pad, and the second contact points are elastically extruded from the second surface to contact the second contact pad, so as to overcome the poor electrical connections between the printed circuit board and the probe head through the interposer due to poor coplanarity of the first contact pads of the printed circuit board.

摘要翻译： 模块化探针卡包括印刷电路板，插入件和探针头，其中印刷电路板具有多个第一接触焊盘，探头具有多个第二接触焊盘。 插入器设置在印刷电路板和探针头之间，其中插入器包括基板和多个弹簧销。 基板具有从第一表面到第二表面的第一表面，第二表面和多个通孔。 弹簧销固定在基板的通孔中。 每个弹簧销具有第一接触点，第二接触点和它们之间的弹簧，由此第一接触点从第一表面弹性挤出以接触第一接触垫，并且第二接触点从 第二表面接触第二接触焊盘，以便克服印刷电路板和探针头之间通过插入器的不良电连接，因为印刷电路板的第一接触焊盘的共面性差。

公开(公告)号：US20060231941A1

公开(公告)日：2006-10-19

申请号：US11228234

申请日：2005-09-19

申请人： Hsiang-Ming Huang ,  Yeong-Ching Chao ,  Yi-Chang Lee ,  An-Hong Liu

发明人： Hsiang-Ming Huang ,  Yeong-Ching Chao ,  Yi-Chang Lee ,  An-Hong Liu

IPC分类号： H01L23/24 ,  H01L23/52

CPC分类号： H01L21/4853 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/85181 ,  H01L2224/92147 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0401

摘要： A pillar grid array package (PGA) includes a substrate, a chip disposed on top of the substrate, and a plurality of stud bumps disposed on bottom of the substrate. The stud bumps are formed in an array and each has a flattened top to electrically connect to a printed circuit board, PCB, by an anisotropic conductive paste to achieve a thin package and to avoid substrate warpage problems of a ball grid array (BGA) during high-temperature reflow processes.

摘要翻译： 支柱阵列封装（PGA）包括衬底，设置在衬底顶部的芯片和设置在衬底底部的多个柱形凸块。 柱形凸起形成为阵列，并且每个具有平坦的顶部，以通过各向异性导电膏电连接到印刷电路板PCB，以实现薄的封装并避免球栅阵列（BGA）的基板翘曲问题 高温回流工艺。

公开(公告)号：US20130069228A1

公开(公告)日：2013-03-21

申请号：US13559087

申请日：2012-07-26

申请人： An-Hong LIU ,  Hung-Hsin Liu ,  Jar-Dar Yang ,  Chi-Chia Huang ,  Yi-Chang Lee ,  Hsiang-Ming Huang

发明人： An-Hong LIU ,  Hung-Hsin Liu ,  Jar-Dar Yang ,  Chi-Chia Huang ,  Yi-Chang Lee ,  Hsiang-Ming Huang

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/16 ,  H01L23/49894 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/13021 ,  H01L2224/14136 ,  H01L2224/73203 ,  H01L2224/81139 ,  H01L2224/92125

摘要： A flip-chip package structure comprising a substrate, a chip, a bump structure and a solder resist is provided. The substrate has a circuit layer disposed on the surface thereof. The chip comprises a central region and two edge regions disposed on the two sides of the central region. The bump structure is disposed on the central region of the chip and faces the substrate. The solder resist is disposed on the substrate to partially cover the circuit layer. The chip is electrically connected to the substrate by the bump structure, and the solder resist is adapted to come into contact with the two edge regions of the chip to support the chip with the bump structure when the chip is disposed on the substrate.

摘要翻译： 提供了包括衬底，芯片，凸块结构和阻焊剂的倒装芯片封装结构。 基板具有设置在其表面上的电路层。 芯片包括设置在中心区域两侧的中心区域和两个边缘区域。 凸块结构设置在芯片的中心区域并面向衬底。 阻焊剂设置在基板上以部分地覆盖电路层。 芯片通过凸块结构电连接到衬底，并且当芯片设置在衬底上时，阻焊层适于与芯片的两个边缘区域接触以支撑具有凸块结构的芯片。