公开(公告)号：US06825684B1

公开(公告)日：2004-11-30

申请号：US10165879

申请日：2002-06-10

申请人： Hyeon-Seag Kim ,  Amit P. Marathe ,  Nian Yang ,  Tien-Chun Yang

发明人： Hyeon-Seag Kim ,  Amit P. Marathe ,  Nian Yang ,  Tien-Chun Yang

IPC分类号： G01R3100

CPC分类号： G01R31/287 ,  H01L22/20

摘要： A method of generating a lifetime projection for semiconductor devices is disclosed. The disclosed method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition. The method also includes determining the median lifetime for semiconductor devices at each of the stress conditions. Further, the method includes calculating a lifetime at each stress condition at which a predetermined percentage of the devices will exceed and extrapolating the lifetime for devices used at operating conditions.

摘要翻译： 公开了一种为半导体器件生成寿命投影的方法。 所公开的方法包括在多于一个应力条件下从多个半导体器件收集寿命信息。 该方法还包括在每个应力条件下确定半导体器件的中值寿命。 此外，该方法包括计算在预定百分比的装置将超过的每个应力条件下的寿命，并且对在操作条件下使用的装置的寿命进行推断。

公开(公告)号：US06812514B1

公开(公告)日：2004-11-02

申请号：US10660420

申请日：2003-09-10

申请人： Nian Yang ,  Zhigang Wang ,  Hyeon-seag Kim

发明人： Nian Yang ,  Zhigang Wang ,  Hyeon-seag Kim

IPC分类号： H01L2976

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A floating gate flash memory device including a substrate including a source region, a drain region and a channel region positioned therebetween; a stack gate including a floating gate electrode, at least one of sidewall/spacers, second sidewalls or a barrier layer, in which the floating gate is positioned above the channel region. The floating gate may be separated from the channel region by one or more of a reverse tunnel dielectric layer, the barrier layer and a pad dielectric layer. The floating gate may be a metal floating gate.

摘要翻译： 一种浮栅闪存器件，包括：衬底，其包括源极区，漏极区和位于其间的沟道区; 包括浮置栅电极的堆叠栅极，侧壁/间隔物，第二侧壁或阻挡层中的至少一个，浮栅位于沟道区的上方。 浮栅可以通过反向隧道介电层，阻挡层和焊盘介电层中的一个或多个与沟道区分离。 浮动栅极可以是金属浮动栅极。

公开(公告)号：US06784061B1

公开(公告)日：2004-08-31

申请号：US10179723

申请日：2002-06-25

申请人： Nian Yang ,  John Jianshi Wang ,  Hyeon-Seag Kim

发明人： Nian Yang ,  John Jianshi Wang ,  Hyeon-Seag Kim

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825

摘要： One aspect of the invention relates to a method of a NOR-type flash memory and associated structure which comprises forming a flash memory array on a semiconductor substrate in a core region of the flash memory. The flash memory array comprises a plurality of flash memory cells which each have a source region and a drain region in the semiconductor substrate. A first portion of a first dielectric layer is formed over the flash memory array, and contact holes in the first dielectric layer are formed down to source regions of flash memory cells in the core region. A trench is then formed in the first dielectric layer and extends between the two contact holes. The contact holes and trench are then filled with a conductive material, thereby electrically coupling together the source regions of the two flash memory cells. A second portion of the first dielectric layer is then formed over the first portion of the first dielectric layer and the trench, thereby embedding the source contacts and trench in within the first dielectric layer.

摘要翻译： 本发明的一个方面涉及NOR型闪速存储器及其相关结构的方法，其包括在闪速存储器的核心区域中的半导体衬底上形成闪存阵列。 闪存阵列包括多个闪存单元，每个闪存单元在半导体衬底中具有源区和漏区。 第一电介质层的第一部分形成在闪速存储器阵列上，并且第一介电层中的接触孔形成为芯区域中的闪存单元的源区。 然后在第一介电层中形成沟槽并在两个接触孔之间延伸。 然后用导电材料填充接触孔和沟槽，从而将两个闪存单元的源极区域电耦合在一起。 然后在第一介电层和沟槽的第一部分上形成第一介电层的第二部分，从而将源极触点和沟槽嵌入第一介电层内。

公开(公告)号：US06660588B1

公开(公告)日：2003-12-09

申请号：US10244229

申请日：2002-09-16

申请人： Nian Yang ,  Zhigang Wang ,  Hyeon-seag Kim

发明人： Nian Yang ,  Zhigang Wang ,  Hyeon-seag Kim

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A process for fabrication of a floating gate flash memory device, and the device made thereby, including providing a semiconductor substrate; forming a pad dielectric layer overlying the substrate; forming a hard mask layer overlying the pad dielectric layer; forming an initial trench through the hard mask layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer; reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lrx, wherein x is at least one; and filling the reduced trench with a floating gate material.

摘要翻译： 一种用于制造浮动栅极闪存器件的方法及其制造的器件，包括提供半导体衬底; 形成覆盖所述基板的焊盘电介质层; 形成覆盖所述焊盘介电层的硬掩模层; 通过所述硬掩模层形成初始沟槽，其中所述初始沟槽具有由所述硬掩模层中的相对的硬掩模侧壁限定的初始横向延伸度; 减小初始沟槽的初始横向范围Li以限定具有减小的横向范围Lrx的减小的沟槽，其中x为至少一个; 并用浮栅材料填充还原的沟槽。

公开(公告)号：US06534363B2

公开(公告)日：2003-03-18

申请号：US09803400

申请日：2001-03-12

申请人： Hyeon-Seag Kim

发明人： Hyeon-Seag Kim

IPC分类号： H01L21336

CPC分类号： H01L21/31662 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

摘要： A method for forming a high voltage gate oxide having a high quality and reliability for use with non-volatile memory devices is provided. Field oxide isolation regions are formed in the top surface of a semiconductor substrate so as to define a first active region, a second active region, and a third active region. A sacrificial oxide layer is formed on the top surface of the semiconductor layer and overlying the first through third active regions. The sacrificial oxide layer is removed from only the first active region. A tunnel oxide layer is formed over the first active region and over the sacrificial oxide layer overlying the second active region and the third active region. A floating gate structure is formed in the first active region. The tunnel oxide layer and the sacrificial oxide layer over the respective second active region and third active region are removed subsequent to forming the floating gate structure. A high voltage gate oxide layer is formed over the second active region and the third active region. The high voltage gate oxide layer is removed from only the third active region. A low voltage gate oxide layer is formed over the third active region. As a result, nitride contamination at the oxide-to-substrate interfaces in the second and third active regions has been eliminated.

摘要翻译： 提供了一种用于形成具有用于非易失性存储器件的高质量和可靠性的高压栅极氧化物的方法。 在半导体衬底的顶表面中形成场氧化物隔离区，以限定第一有源区，第二有源区和第三有源区。 牺牲氧化物层形成在半导体层的顶表面上并覆盖第一至第三有源区。 牺牲氧化物层仅从第一活性区域去除。 隧道氧化物层形成在第一有源区上方，覆盖在第二有源区和第三有源区上方的牺牲氧化物层上。 在第一有源区中形成浮栅结构。 在形成浮栅结构之后，去除相应的第二有源区和第三有源区上的隧道氧化物层和牺牲氧化物层。 在第二有源区和第三有源区上形成高压栅氧化层。 仅从第三有源区域去除高电压栅极氧化物层。 在第三有源区上形成低电压栅氧化层。 结果，消除了第二和第三活性区域中的氧化物到衬底界面处的氮化物污染。

公开(公告)号：US06365450B1

公开(公告)日：2002-04-02

申请号：US09809706

申请日：2001-03-15

申请人： Hyeon-Seag Kim

发明人： Hyeon-Seag Kim

IPC分类号： H01L218238

CPC分类号： H01L21/823842

摘要： For fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a PMOS gate dielectric is formed on the semiconductor substrate, and a PMOS dummy gate electrode is formed on the gate dielectric. A P-type dopant is implanted into exposed regions of the semiconductor substrate to form a PMOS drain junction and a PMOS source junction. A thermal anneal is performed to activate the drain and source P-type dopant within the drain and source junctions. A PMOS drain silicide is formed with the drain junction, and a PMOS source silicide is formed with the source junction, in a silicidation process. An insulating material is deposited to surround the dummy gate electrode and the gate dielectric. The dummy gate electrode is etched away to form a PMOS gate electrode opening surrounded by the insulating material. The gate electrode opening is filled with a metal oxide material to form a PMOS metal oxide gate electrode after the thermal anneal process for activating the drain and source P-type dopant within the drain and source junctions and after the silicidation process for forming the drain and source silicides, to minimize degradation of the metal oxide gate electrode. In another aspect of the present invention, an insulating material is deposited on top of the metal oxide gate electrode to encapsulate the metal oxide gate electrode before performing a thermal anneal with hydrogen gas to prevent exposure of the metal oxide gate electrode to the hydrogen gas to further minimize degradation of the metal oxide gate electrode.

摘要翻译： 为了在半导体衬底上制造PMOS（P沟道金属氧化物半导体）场效应晶体管，在半导体衬底上形成PMOS栅极电介质，在栅极电介质上形成PMOS虚拟栅电极。 将P型掺杂剂注入到半导体衬底的暴露区域中以形成PMOS漏极结和PMOS源极结。 执行热退火以激活漏极和源极结内的漏极和源极P型掺杂剂。 在漏极结中形成PMOS漏极硅化物，在硅化处理中形成PMOS源硅化物与源极结。 沉积绝缘材料以包围虚拟栅极电极和栅极电介质。 蚀刻掉伪栅电极以形成被绝缘材料包围的PMOS栅电极开口。 栅极电极开口填充有金属氧化物材料，以在热退火工艺之后形成PMOS金属氧化物栅电极，用于激活漏极和源极结内的漏极和源极P型掺杂剂，以及用于形成漏极的硅化工艺 源极硅化物，以最小化金属氧化物栅电极的劣化。 在本发明的另一方面，在金属氧化物栅电极的顶部上沉积绝缘材料，以在与氢气进行热退火之前封装金属氧化物栅电极，以防止金属氧化物栅极暴露于氢气到 进一步最小化金属氧化物栅电极的劣化。

公开(公告)号：US06861696B1

公开(公告)日：2005-03-01

申请号：US10429140

申请日：2003-05-03

申请人： Hyeon-Seag Kim ,  Nian Yang ,  Munseork Choi

发明人： Hyeon-Seag Kim ,  Nian Yang ,  Munseork Choi

IPC分类号： H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7923

摘要： According to one exemplary embodiment, a two-bit memory cell situated over a substrate comprises a tunnel oxide layer situated over the substrate. The two-bit memory cell further comprises a first spacer and a second spacer situated over the tunnel oxide layer, where the first spacer is a first data bit storage location in the two-bit memory cell and the second spacer is a second data bit storage location in the two-bit memory cell. The first spacer and the second spacer may be, for example, silicon nitride or polycrystalline silicon. According to this exemplary embodiment, the two-bit memory cell further comprises an oxide layer situated between the first spacer and the second spacer. The two-bit memory cell further comprises a control gate situated over the oxide layer.

摘要翻译： 根据一个示例性实施例，位于衬底上方的两位存储器单元包括位于衬底上方的隧道氧化物层。 两位存储单元还包括位于隧道氧化物层上的第一间隔物和第二隔离物，其中第一间隔物是两位存储单元中的第一数据位存储位置，第二隔离物是第二数据位存储 位置在两位存储单元中。 第一间隔物和第二间隔物可以是例如氮化硅或多晶硅。 根据该示例性实施例，两比特存储单元还包括位于第一间隔物和第二间隔物之间​​的氧化物层。 两比特存储单元进一步包括位于氧化物层上方的控制栅极。

公开(公告)号：US06784682B1

公开(公告)日：2004-08-31

申请号：US10113259

申请日：2002-03-28

申请人： Tien-Chun Yang ,  Nian Yang ,  Hyeon-Seag Kim

发明人： Tien-Chun Yang ,  Nian Yang ,  Hyeon-Seag Kim

IPC分类号： G01R3126

CPC分类号： G01R31/2648

摘要： A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current profile is recorded. A comparison of current profiles obtained for the two types of structures may indicate the presence and/or extent of STI corner effects. More specifically, a steeper slope for a normalized current versus time plot for an STI edge intensive structure (500) compared to a slope of a normalized plot of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness is observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.

摘要翻译： 一种用于测试包括浅沟槽隔离（STI）边缘结构的半导体的方法和装置。 边缘密集的浅沟槽隔离结构（500）耦合到电压源（310）并且记录电流分布。 在同一晶片上的平面结构（600）耦合到电压源并且记录电流分布。 对于两种类型的结构获得的当前轮廓的比较可以指示STI拐角效应的存在和/或程度。 更具体地，与平面结构（600）的归一化图的斜率相比，用于STI边缘密集结构（500）的归一化电流对时间图的更陡峭的斜率表示STI拐角中的电子捕获速率增加， 这可能表明STI拐角太薄。 以这种新颖的方式，在非破坏性电气测试过程中观察到STI拐角厚度，从而导致使用STI工艺的半导体的更高的质量和更高的可靠性。

公开(公告)号：US06646326B1

公开(公告)日：2003-11-11

申请号：US09714361

申请日：2000-11-15

申请人： Hyeon-Seag Kim ,  Jongwook Kye

发明人： Hyeon-Seag Kim ,  Jongwook Kye

IPC分类号： H01L2906

CPC分类号： H01L27/11521 ,  H01L21/28114 ,  H01L21/823425 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/6659 ,  H01L29/66825

摘要： A method and system for providing a semiconductor device on a substrate are disclosed. The method and system include providing a tunneling barrier on the substrate and providing at least one gate on the tunneling barrier. The at least one of gate includes a first edge, a second edge and a base. The method and system further include providing a source and/or a drain for the at least one gate. The source and/or a drain are in proximity to the first edge or the first and second edges of the at least one gate. The at least one gate, the source and/or drain or both the at least one gate and the source and/or drain are configured such that source and/or drain do not substantially overlap the at least one gate at the base of the at least one gate.

摘要翻译： 公开了一种在衬底上提供半导体器件的方法和系统。 该方法和系统包括在衬底上提供隧道势垒并在隧道势垒上提供至少一个栅极。 栅极中的至少一个包括第一边缘，第二边缘和基底。 所述方法和系统还包括为所述至少一个门提供源极和/或漏极。 源极和/或漏极位于至少一个栅极的第一边缘或第一和第二边缘附近。 所述至少一个栅极，源极和/或漏极或者至少一个栅极和源极和/或漏极都被构造成使得源极和/或漏极基本上不与位于所述源极和/或漏极的基极处的至少一个栅极重叠 至少一个门。

公开(公告)号：US06376323B1

公开(公告)日：2002-04-23

申请号：US09825819

申请日：2001-04-04

申请人： Hyeon-Seag Kim ,  Joong Jeon

发明人： Hyeon-Seag Kim ,  Joong Jeon

IPC分类号： H01L21331

CPC分类号： H01L21/28035 ,  H01L21/823842 ,  H01L21/823857

摘要： For fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a layer of gate dielectric material containing nitrogen is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A first P-type dopant, such as boron for example, is implanted into a first region of the layer of gate electrode material disposed over a first active device area of the semiconductor substrate. The first region of the layer of gate electrode material is patterned to form a PMOS gate electrode. The layer of gate dielectric material is patterned to form a PMOS gate dielectric disposed under the PMOS gate electrode. A second P-type dopant, such as boron fluoride (BF2) for example, is implanted into the PMOS gate electrode and into the exposed regions of the first active device area of the semiconductor substrate to form a drain extension junction and a source extension junction of the PMOS field effect transistor. The boron as the first P-type dopant is a lighter dopant than boron fluoride (BF2) and thus distributes more evenly throughout the layer of gate electrode material. The nitrogen within the gate dielectric material below the layer of gate electrode material prevents diffusion of the boron out of the gate electrode material and into the gate dielectric. Thus, a depletion region is less likely to form toward the bottom of the gate electrode near the gate dielectric. The boron fluoride (BF2) as the second P-type dopant that is relatively heavier is used to form shallow drain and source extensions to minimize short channel effects of the PMOS field effect transistor.

摘要翻译： 为了在半导体衬底上制造PMOS（P沟道金属氧化物半导体）场效应晶体管，在半导体衬底上沉积含有氮的栅极介电材料层，并且在栅极电介质层上沉积一层栅电极材料 材料。 诸如硼的第一P型掺杂剂例如注入设置在半导体衬底的第一有源器件区域上的栅电极层的第一区域中。 图案化栅极材料层的第一区域以形成PMOS栅电极。 栅极介电材料层被图案化以形成设置在PMOS栅电极下方的PMOS栅极电介质。 例如，诸如氟化硼（BF 2）的第二P型掺杂剂注入PMOS栅电极并注入到半导体衬底的第一有源器件区域的暴露区域中，以形成漏极延伸结和源极延伸结 的PMOS场效应晶体管。 作为第一P型掺杂剂的硼是比氟化硼（BF 2）更轻的掺杂剂，因此更均匀地分配在整个栅极电极材料层上。 位于栅电极材料层下方的栅极电介质材料内的氮阻止硼从栅电极材料中扩散并进入栅极电介质。 因此，耗尽区域不太可能在栅极电介质附近的栅极电极的底部形成。 用作相对较重的第二P型掺杂剂的氟化硼（BF 2）用于形成浅的漏极和源极延伸，以最小化PMOS场效应晶体管的短沟道效应。