公开(公告)号：US20120045901A1

公开(公告)日：2012-02-23

申请号：US13212349

申请日：2011-08-18

申请人： JONG-HYUK KIM ,  Keon-Soo Kim ,  Kwang-Shik Shin ,  Hyun-Chul Back ,  Seong-Soon Cho ,  Young-Bae Yoon ,  Jung-Hwan Park

发明人： JONG-HYUK KIM ,  Keon-Soo Kim ,  Kwang-Shik Shin ,  Hyun-Chul Back ,  Seong-Soon Cho ,  Young-Bae Yoon ,  Jung-Hwan Park

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76816

摘要： In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.

摘要翻译： 在形成图案结构的方法中，通过使用牺牲掩模图案和掩模图案的连接部分的双重图案化工艺来形成半导体器件的节点分离线的截止部分，从而改善对准边缘 。 掩模图案和牺牲掩模图案之间的对准边缘增加到牺牲掩模图案的连接部分的长度的量。 与节点分离线相邻的线包括向分离线的截止部分突出的突出部分。

公开(公告)号：US08759224B2

公开(公告)日：2014-06-24

申请号：US13212349

申请日：2011-08-18

申请人： Jong-Hyuk Kim ,  Keon-Soo Kim ,  Kwang-Shik Shin ,  Hyun-Chul Back ,  Seong-Soon Cho ,  Young-Bae Yoon ,  Jung-Hwan Park

发明人： Jong-Hyuk Kim ,  Keon-Soo Kim ,  Kwang-Shik Shin ,  Hyun-Chul Back ,  Seong-Soon Cho ,  Young-Bae Yoon ,  Jung-Hwan Park

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76816

摘要： In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.

摘要翻译： 在形成图案结构的方法中，通过使用牺牲掩模图案和掩模图案的连接部分的双重图案化工艺来形成半导体器件的节点分离线的截止部分，从而提高对准边缘 。 掩模图案和牺牲掩模图案之间的对准边缘增加到牺牲掩模图案的连接部分的长度的量。 与节点分离线相邻的线包括向分离线的截止部分突出的突出部分。

公开(公告)号：US08405158B2

公开(公告)日：2013-03-26

申请号：US12832373

申请日：2010-07-08

申请人： Young-Bae Yoon ,  Jong-Hyuk Kim ,  Keonsoo Kim ,  Youngseop Rah ,  Yoonmoon Park

发明人： Young-Bae Yoon ,  Jong-Hyuk Kim ,  Keonsoo Kim ,  Youngseop Rah ,  Yoonmoon Park

IPC分类号： H01L27/088 ,  H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/11519

摘要： A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other.

摘要翻译： 一种半导体存储器件及其制造方法，该器件包括串联结构，串联结构包括两个或多个相邻的串选择晶体管，它们在第一方向上彼此串联连接，并且在第二方向上相互间隔开 所述第一方向，所述两个或更多个串选择晶体管具有不同的阈值电压; 串选择线，串串选择线，连接串结构的相邻串选择晶体管沿第二方向; 以及电连接两个或更多个相邻串结构的位线，其中在第二方向上的相邻串选择晶体管之间的器件隔离层具有凹陷区域，并且串选择晶体管的相应侧上的凹陷区域的轮廓与每个不同 其他。

公开(公告)号：US20110038211A1

公开(公告)日：2011-02-17

申请号：US12832373

申请日：2010-07-08

申请人： Young-Bae Yoon ,  Jong-Hyuk Kim ,  Keonsoo Kim ,  Youngseop Rah ,  Yoonmoon Park

发明人： Young-Bae Yoon ,  Jong-Hyuk Kim ,  Keonsoo Kim ,  Youngseop Rah ,  Yoonmoon Park

IPC分类号： G11C16/04 ,  H01L27/088

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/11519

摘要： A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other.

摘要翻译： 一种半导体存储器件及其制造方法，该器件包括串联结构，串联结构包括两个或更多个相邻的串选择晶体管，它们在第一方向上彼此串联连接并且沿第二方向相互间隔开 所述第一方向，所述两个或更多个串选择晶体管具有不同的阈值电压; 串选择线，串串选择线，连接串结构的相邻串选择晶体管沿第二方向; 以及电连接两个或更多个相邻串结构的位线，其中在第二方向上的相邻串选择晶体管之间的器件隔离层具有凹陷区域，并且串选择晶体管的相应侧上的凹陷区域的轮廓与每个不同 其他。

公开(公告)号：US10482964B2

公开(公告)日：2019-11-19

申请号：US16040837

申请日：2018-07-20

申请人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

发明人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

IPC分类号： G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L49/02

摘要： Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US10049744B2

公开(公告)日：2018-08-14

申请号：US15383213

申请日：2016-12-19

申请人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

发明人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

IPC分类号： H01L29/788 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06

摘要： Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US10741571B2

公开(公告)日：2020-08-11

申请号：US15401486

申请日：2017-01-09

申请人： Young-Bae Yoon ,  Joong-Shik Shin ,  Kwang-Ho Kim ,  Hyun-Mog Park

发明人： Young-Bae Yoon ,  Joong-Shik Shin ,  Kwang-Ho Kim ,  Hyun-Mog Park

IPC分类号： H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11575

摘要： A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

公开(公告)号：US08652928B2

公开(公告)日：2014-02-18

申请号：US13240883

申请日：2011-09-22

申请人： Young-Bae Yoon ,  Jeong-Dong Choe ,  Dong-Hoon Jang ,  Ki-Hyun Kim

发明人： Young-Bae Yoon ,  Jeong-Dong Choe ,  Dong-Hoon Jang ,  Ki-Hyun Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/823456 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.

摘要翻译： 半导体器件包括具有第一区域和第二区域的衬底，第一区域中的第一晶体管，第二区域中的第二晶体管，第一区域和第二区域之间的隔离层，以及至少一个掩埋屏蔽结构 在隔离层上。

公开(公告)号：US08059469B2

公开(公告)日：2011-11-15

申请号：US12481916

申请日：2009-06-10

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

IPC分类号： G11C11/34

CPC分类号： H01L27/11573 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L29/78

摘要： A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

摘要翻译： 半导体器件包括限定在衬底中的驱动有源区和设置在驱动有源区的至少三个驱动晶体管。 驱动晶体管共享一个共同的源极/漏极，并且每个驱动晶体管包括彼此独立的各个源极/漏极。 公共源极/漏极和各个源极/漏极设置在驱动有源区域中。

公开(公告)号：US20090230456A1

公开(公告)日：2009-09-17

申请号：US12382232

申请日：2009-03-11

申请人： Young-Bae Yoon ,  Jeong-Dong Choe ,  Dong-Hoon Jang ,  Ki-Hyun Kim

发明人： Young-Bae Yoon ,  Jeong-Dong Choe ,  Dong-Hoon Jang ,  Ki-Hyun Kim

IPC分类号： H01L29/788 ,  H01L27/06

CPC分类号： H01L21/823481 ,  H01L21/823456 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.

摘要翻译： 半导体器件包括具有第一区域和第二区域的衬底，第一区域中的第一晶体管，第二区域中的第二晶体管，第一区域和第二区域之间的隔离层，以及至少一个掩埋屏蔽结构 在隔离层上。