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    Flash memories having at least one resistance pattern on gate pattern and methods of fabricating the same
    3.
    发明申请
    Flash memories having at least one resistance pattern on gate pattern and methods of fabricating the same 审中-公开
    在栅极图案上具有至少一个电阻图案的闪存及其制造方法

    公开(公告)号：US20060138559A1

    公开(公告)日：2006-06-29

    申请号：US11317595

    申请日：2005-12-23

    申请人： Dong-Jun Lee ,  Keon-Soo Kim ,  Hyun-Chul Back ,  Seong-Soon Cho

    发明人： Dong-Jun Lee ,  Keon-Soo Kim ,  Hyun-Chul Back ,  Seong-Soon Cho

    IPC分类号： H01L29/00 ,  H01L21/8234

    CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11543

    摘要： Flash memories and methods of manufacturing the same provide at least one resistance pattern on a gate pattern, and are capable of increasing a process margin in the semiconductor fabrication process. Gate patterns and bit line patterns are sequentially formed in a cell array region and a peripheral circuit region of a semiconductor substrate. A bit line interlayer insulating layer is disposed to cover the bit line patterns. At least one resistance pattern is disposed on the bit line interlayer insulating layer in the cell array region of the semiconductor substrate. A planarized interlayer insulating layer is formed on the bit line interlayer insulating layer to cover the resistance pattern. Interconnection lines such as metal interconnection lines are formed on the planarized interlayer insulating layer in the cell array region and the peripheral circuit region of the semiconductor substrate.

    摘要翻译： 闪存及其制造方法在栅极图案上提供至少一个电阻图案，并且能够增加半导体制造工艺中的工艺裕度。 栅极图案和位线图案依次形成在半导体衬底的单元阵列区域和外围电路区域中。 布置位线层间绝缘层以覆盖位线图形。 在半导体衬底的单元阵列区域中的位线层间绝缘层上设置至少一个电阻图案。 平面化层间绝缘层形成在位线层间绝缘层上以覆盖电阻图形。 互连线如金属互连线形成在电池阵列区域和半导体衬底的外围电路区域的平坦化层间绝缘层上。

    NAND-type flash memory devices and fabrication methods thereof
    4.
    发明授权
    NAND-type flash memory devices and fabrication methods thereof 有权
    NAND型闪存器件及其制造方法

    公开(公告)号：US07339242B2

    公开(公告)日：2008-03-04

    申请号：US11360112

    申请日：2006-02-22

    申请人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

    发明人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

    IPC分类号： H01L29/76

    CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

    摘要： In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs are formed of the same conductive layer through the same process. Also, metal interconnections including bit lines, a cell metal interconnection, a peripheral gate interconnection, and peripheral metal interconnections directly connected to the plugs may be formed of the same metal layer through the same process. Accordingly, the interconnection structure such as the plugs and the metal interconnections is simplified and thus the process of their formation is simplified.

    摘要翻译： 在一个实施例中，存储器件包括具有单元有源区和外围有源区的半导体衬底。 包括位线接触插头，公共源极线，外围栅极互连接触插头和外围金属互连接触插头的插头通过相同的工艺由相同的导电层形成。 此外，包括位线，电池金属互连，外围栅极互连和直接连接到插塞的外围金属互连的金属互连可以通过相同的工艺由相同的金属层形成。 因此，诸如插头和金属互连之类的互连结构被简化，因此它们的形成过程被简化。

    Method of manufacturing an integrated circuit device
    5.
    发明授权
    Method of manufacturing an integrated circuit device 失效
    集成电路器件的制造方法

    公开(公告)号：US08642438B2

    公开(公告)日：2014-02-04

    申请号：US13324035

    申请日：2011-12-13

    申请人： Young-Ho Lee ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

    发明人： Young-Ho Lee ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

    IPC分类号： H01L21/20 ,  H01L21/00

    CPC分类号： H01L27/0629 ,  H01L27/11531 ,  H01L28/20

    摘要： In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

    摘要翻译： 在集成电路器件及其制造方法中，电阻器图案位于衬底的器件隔离层上。 电阻器图案包括位于器件隔离层的凹部中的电阻体，以及与电阻体接触并连接在凹部的周围的器件隔离层上的连接器。 连接器具有在上部具有低于电阻体的电阻的金属硅化物图案。 栅极图案位于衬底的有源区上，并且在上部包括金属硅化物图案。 提供电阻器互连以与电阻器图案的连接器接触。 连接器和电阻器互连之间的接触电阻降低。

    METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE
    6.
    发明申请
    METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE 失效
    制造集成电路设备的方法

    公开(公告)号：US20120178234A1

    公开(公告)日：2012-07-12

    申请号：US13324035

    申请日：2011-12-13

    申请人： Young-Ho LEE ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

    发明人： Young-Ho LEE ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

    IPC分类号： H01L21/8239

    CPC分类号： H01L27/0629 ,  H01L27/11531 ,  H01L28/20

    摘要： In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

    摘要翻译： 在集成电路器件及其制造方法中，电阻器图案位于衬底的器件隔离层上。 电阻器图案包括位于器件隔离层的凹部中的电阻体，以及与电阻体接触并连接在凹部的周围的器件隔离层上的连接器。 连接器具有在上部具有低于电阻体的电阻的金属硅化物图案。 栅极图案位于衬底的有源区上，并且在上部包括金属硅化物图案。 提供电阻器互连以与电阻器图案的连接器接触。 连接器和电阻器互连之间的接触电阻降低。

    NAND-type flash memory devices and fabrication methods thereof
    7.
    发明申请
    NAND-type flash memory devices and fabrication methods thereof 有权
    NAND型闪存器件及其制造方法

    公开(公告)号：US20060186485A1

    公开(公告)日：2006-08-24

    申请号：US11360112

    申请日：2006-02-22

    申请人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

    发明人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

    IPC分类号： H01L29/76

    CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

    摘要： In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs are formed of the same conductive layer through the same process. Also, metal interconnections including bit lines, a cell metal interconnection, a peripheral gate interconnection, and peripheral metal interconnections directly connected to the plugs may be formed of the same metal layer through the same process. Accordingly, the interconnection structure such as the plugs and the metal interconnections is simplified and thus the process of their formation is simplified.

    摘要翻译： 在一个实施例中，存储器件包括具有单元有源区和外围有源区的半导体衬底。 包括位线接触插头，公共源极线，外围栅极互连接触插头和外围金属互连接触插头的插头通过相同的工艺由相同的导电层形成。 此外，包括位线，电池金属互连，外围栅极互连和直接连接到插塞的外围金属互连的金属互连可以通过相同的工艺由相同的金属层形成。 因此，诸如插头和金属互连之类的互连结构被简化，因此它们的形成过程被简化。

    Structure nonvolatile semiconductor memory cell array and method for fabricating same
    9.
    发明授权
    Structure nonvolatile semiconductor memory cell array and method for fabricating same 有权
    结构非易失性半导体存储单元阵列及其制造方法

    公开(公告)号：US6130838A

    公开(公告)日：2000-10-10

    申请号：US132685

    申请日：1998-08-12

    申请人： Keon-Soo Kim ,  Jeong-Hyuk Choi

    发明人： Keon-Soo Kim ,  Jeong-Hyuk Choi

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  G11C16/04

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A nonvolatile semiconductor memory cell array is shown which is composed of a plurality of unit cell-arrays arranged in a repeating pattern. Each of the unit cell-arrays includes a first plurality of cell transistors having control gates coupled in common to a first word line and a second plurality of cell transistors having control gates coupled in common to a second word line. The two word lines are arranged in parallel to one another and perpendicular to a bit line. The bit line is connected in common with drains of both the first and second plurality of cell transistors through a bit line contact. A pair of source lines is arranged along each side of the bit line and parallel to the bit line. Each source line is coupled to one transistor from each of the first and second pluralities of cell transistors through a source line contact.

    摘要翻译： 示出了由以重复图案排列的多个单元阵列组成的非易失性半导体存储单元阵列。 每个单元阵列包括具有共同耦合到第一字线的控制栅极的第一多个单元晶体管和具有共同耦合到第二字线的控制栅极的第二多个单元晶体管。 两条字线彼此平行并垂直于位线排列。 位线通过位线接触与第一和第二多个单元晶体管的漏极相连。 一对源极线沿位线的每一侧排列并且平行于位线。 每个源极线通过源极线接触耦合到来自第一和第二多个单元晶体管中的每一个的一个晶体管。

    Methods of forming EEPROM memory cells having uniformly thick tunnelling oxide layers
    10.
    发明授权
    Methods of forming EEPROM memory cells having uniformly thick tunnelling oxide layers 失效
    形成具有均匀厚度的隧道氧化物层的EEPROM存储单元的方法

    公开(公告)号：US5888871A

    公开(公告)日：1999-03-30

    申请号：US774100

    申请日：1996-12-24

    申请人： Myoung-Kwan Cho ,  Keon-Soo Kim

    发明人： Myoung-Kwan Cho ,  Keon-Soo Kim

    IPC分类号： H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： Methods of forming EEPROM memory cells having uniformly thick tunnelling oxide layers include the steps of forming a preliminary field oxide isolation region of first thickness at a face of a semiconductor substrate of first conductivity type (e.g., P-type) and then forming a tunneling oxide layer on the face, adjacent the preliminary field oxide isolation region. The memory cell's drain region dopants are then implanted through the preliminary field oxide isolation region and into the substrate to form a preliminary drain region of second conductivity type. The preliminary field oxide isolation region is then grown to a second thickness greater than the first thickness by oxidizing the portion of the substrate containing the implanted dopants, to form a final field oxide isolation region which may have a thickness of about 2000 .ANG.. To prevent unwanted growth of the tunnelling oxide layer, a silicon nitride layer is preferably patterned on the tunnelling oxide layer and used as an oxidation mask during the step of growing the preliminary field oxide isolation region to a second thickness. The silicon nitride mask is then removed and then a floating gate electrode and insulated control electrode are patterned on the tunnelling oxide layer and channel region to complete the memory cell.

    摘要翻译： 形成具有均匀厚的隧道氧化物层的EEPROM存储单元的方法包括以下步骤：在第一导电类型的半导体衬底（例如，P型）的表面上形成第一厚度的预备场氧化物隔离区，然后形成隧道氧化物 层在面上，毗邻初步场氧化物隔离区。 然后通过预备场氧化物隔离区域将衬底中的存储单元的漏极区掺杂物注入到衬底中以形成第二导电类型的初级漏区。 然后通过氧化含有注入的掺杂剂的衬底的部分，将初始场氧化物隔离区域生长到大于第一厚度的第二厚度，以形成最终的场氧化物隔离区域，其可以具有约2000的厚度。 为了防止隧道氧化物层的不期望的生长，优选在隧道氧化物层上图案化氮化硅层，并且在将预备场氧化物隔离区域生长至第二厚度的步骤期间用作氧化掩模。 然后去除氮化硅掩模，然后在隧道氧化物层和沟道区上图案化浮栅电极和绝缘控制电极，以完成存储单元。