Clock and data recovery circuit from an N-pulse amplitude modulation signal

    公开(公告)号:US12166491B2

    公开(公告)日:2024-12-10

    申请号:US18064588

    申请日:2022-12-12

    Abstract: An apparatus and a method for recovering clock and data from a multilevel pulse amplitude modulated signal received as input signal is suggested. The apparatus comprises a phase detector, a low-pass filter, a voltage-controlled oscillator, and a feedback loop forming a CDR loop. The voltage-controlled oscillator outputs a clock signal that is provided to the phase detector. The phase detector receives an MSB signal from a sampler. The apparatus also comprises an interleave circuit configured to receive the input signal and to generate two output signals having a smaller symbol rate than the input signal. The apparatus further comprises a logical gate configured to receive the output signals from the interleave circuit and to generate an enable signal for the phase detector indicating symmetrical transitions in the input signal. Lastly, the apparatus comprises a converter converting the output signals from the interleave circuit into an MSB and an LSB bit stream.

    AMPLIFICATION CIRCUIT WITH READ/WRITE CIRCUIT

    公开(公告)号:US20190068151A1

    公开(公告)日:2019-02-28

    申请号:US16106108

    申请日:2018-08-21

    Abstract: The invention relates to an amplification circuit (100), comprising: a VGA (2), an AGC loop (10) for automatically controlling the gain of the VGA (2), a switching circuit (14) for switching between an AGC mode, in which the gain of the VGA (2) is automatically controlled by an output signal of the AGC loop (10) and a manual gain control, MGC, mode, in which the gain of the VGA (2) can be manually controlled by an input signal, and a read/write circuit (30) with a contact (31) for connection to a peripheral system, wherein the read/write circuit (30) is configured, in the MGC mode, to provide the input signal from the contact (31) via a write-mode path (32) to the VGA (2), and, in the AGC mode, to provide the output signal of the AGC loop (10) via a read-mode path (33) on the contact (31).

    CMOS-COMPATIBLE GERMANIUM TUNABLE LASER
    10.
    发明申请
    CMOS-COMPATIBLE GERMANIUM TUNABLE LASER 有权
    CMOS兼容GERMANIUM TUNABLE激光

    公开(公告)号:US20150063382A1

    公开(公告)日:2015-03-05

    申请号:US14377032

    申请日:2013-02-11

    CPC classification number: H01S5/3201 H01L33/34 H01S5/021 H01S5/3223

    Abstract: A semiconductor light emitter device, comprising a substrate, an active layer made of Germanium, which is configured to emit light under application of an operating voltage to the semiconductor light emitter device, wherein a gap is arranged on the substrate, which extends between two bridgeposts laterally spaced from each other, the active layer is arranged on the bridgeposts and bridges the gap, and wherein the semiconductor light emitter device comprises a stressor layer, which induces a tensile strain in the active layer above the gap.

    Abstract translation: 一种半导体光发射器件,包括衬底,由锗制成的有源层,其被配置为在施加工作电压的情况下向所述半导体发光器件发光,其中在所述衬底上布置有间隙,所述间隙在两个桥梁之间延伸 有源层被布置在桥梁上并且桥接间隙,并且其中半导体光发射器件包括应力层,其在空隙上方的有源层中引起拉伸应变。

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