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    Semiconductor nanostructures, semiconductor devices, and methods of making same
    1.
    发明授权
    Semiconductor nanostructures, semiconductor devices, and methods of making same 有权
    半导体纳米结构，半导体器件及其制造方法

    公开(公告)号：US08362582B2

    公开(公告)日：2013-01-29

    申请号：US13041754

    申请日：2011-03-07

    Applicant: Joerg Appenzeller ,  Supratik Guha ,  Emanuel Tutuc

    Inventor： Joerg Appenzeller ,  Supratik Guha ,  Emanuel Tutuc

    IPC: H01L31/058

    CPC classification number: H01L21/30604 ,  B82Y10/00 ,  H01L21/02603 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1041 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

    Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

    Abstract translation: 提供了一种半导体结构，其包括沿纵向轴线布置的多个部分。 优选地，半导体结构包括位于中间部分的相对端的中间部分和两个端子部分。 具有第一掺杂剂浓度的半导体芯片优选地沿着纵向轴线延伸通过中间部分和两个端子部分。 具有第二较高掺杂剂浓度的半导体壳体优选地环绕半导体结构的两个端子部分但不在中间部分处的半导体芯体的一部分。 特别优选的是，半导体结构是具有不大于100nm的横截面尺寸的纳米结构。

    CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT
    3.
    发明申请
    CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT 失效
    基于碳纳米管的集成半导体电路

    公开(公告)号：US20110263101A1

    公开(公告)日：2011-10-27

    申请号：US13170525

    申请日：2011-06-28

    Applicant: Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

    Inventor： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

    IPC: H01L21/20 ,  B82Y40/00

    CPC classification number: H01L51/0541 ,  B82Y10/00 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/75 ,  Y10S977/751 ,  Y10S977/752

    Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

    Abstract translation: 在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。 可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过电介质层对两个器件区域之间的电介质层进行电偏置 碳纳米管。 碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

    Core-shell nanowire transistor
    4.
    发明授权
    Core-shell nanowire transistor 有权
    核壳纳米线晶体管

    公开(公告)号：US07948050B2

    公开(公告)日：2011-05-24

    申请号：US11622358

    申请日：2007-01-11

    Applicant: Joerg Appenzeller ,  Supratik Guha ,  Emanuel Tutuc

    Inventor： Joerg Appenzeller ,  Supratik Guha ,  Emanuel Tutuc

    IPC: H01L31/06

    CPC classification number: H01L21/30604 ,  B82Y10/00 ,  H01L21/02603 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1041 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

    Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

    Abstract translation: 提供了一种半导体结构，其包括沿纵向轴线布置的多个部分。 优选地，半导体结构包括位于中间部分的相对端的中间部分和两个端子部分。 具有第一掺杂剂浓度的半导体芯片优选地沿着纵向轴线延伸通过中间部分和两个端子部分。 具有第二较高掺杂剂浓度的半导体壳体优选地环绕半导体结构的两个端子部分但不在中间部分处的半导体芯体的一部分。 特别优选的是，半导体结构是具有不大于100nm的横截面尺寸的纳米结构。

    CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT
    5.
    发明申请
    CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT 有权
    基于碳纳米管的集成半导体电路

    公开(公告)号：US20100295025A1

    公开(公告)日：2010-11-25

    申请号：US12850259

    申请日：2010-08-04

    Applicant: Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

    Inventor： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

    IPC: H01L27/11 ,  H01L21/8244

    CPC classification number: H01L51/0541 ,  B82Y10/00 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/75 ,  Y10S977/751 ,  Y10S977/752

    Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

    Abstract translation: 在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。 可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过介电层在两个器件区域之间电气偏置区域 碳纳米管。 碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

    Method for fabricating a nanotube field effect transistor
    9.
    发明授权
    Method for fabricating a nanotube field effect transistor 失效
    纳米管场效应晶体管的制造方法

    公开(公告)号：US07482232B2

    公开(公告)日：2009-01-27

    申请号：US11553331

    申请日：2006-10-26

    Applicant: Joerg Appenzeller ,  Phaedon Avouris ,  Yu-Ming Lin

    Inventor： Joerg Appenzeller ,  Phaedon Avouris ,  Yu-Ming Lin

    IPC: H01L29/76

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  Y10S977/721

    Abstract: The method includes forming a 1-10000 nm thick SiO2, HfO2, Al2O3 and/or quartz gate dielectric on an Si back gate. An Al or Mo gate electrode is formed on the gate dielectric. An Al2O3 insulating layer is formed over the gate electrode. A C, Si, GaAs, InP, and/or InGaAs nanotube is formed on the insulating layer and gate dielectric. The nanotube has a central region on the insulating layer above the gate electrode and first and second ends on the gate dielectric. A source is formed on the first end and spaced from the central region and gate electrode by a first peripheral region. A drain is formed on the second end and spaced from the central region and gate electrode by a second peripheral region. The first and second peripheral regions are doped with Cl2, Br2, K, Na, or a molecule of polyethylenimine using wet deposition or evaporation.

    Abstract translation: 该方法包括在Si背栅上形成1-10000nm厚的SiO 2，HfO 2，Al 2 O 3和/或石英栅极电介质。 在栅极电介质上形成Al或Mo栅电极。 在栅电极上形成Al 2 O 3绝缘层。 在绝缘层和栅极电介质上形成C，Si，GaAs，InP和/或InGaAs纳米管。 纳米管在栅电极上方的绝缘层上的中心区域和栅电介质上的第一和第二端。 源极在第一端部上形成并且通​​过第一周边区域与中心区域和栅电极间隔开。 在第二端形成漏极，并且通过第二周边区域与中心区域和栅电极间隔开。 第一和第二周边区域使用湿沉积或蒸发掺杂有Cl 2，Br 2，K，Na或分子的聚乙烯亚胺。

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