公开(公告)号：US07091533B2

公开(公告)日：2006-08-15

申请号：US10842810

申请日：2004-05-11

申请人： Jenö Tihanyi ,  Gerald Deboy

发明人： Jenö Tihanyi ,  Gerald Deboy

IPC分类号： H01L31/062

CPC分类号： H01L29/7824 ,  H01L29/0634 ,  H01L29/8086 ,  H01L29/872

摘要： The invention relates to a semiconductor component, in which regions of the conduction type opposite to the conduction type of the drift zone are incorporated in the drift zone and also in the region of the active zones.

摘要翻译： 本发明涉及一种半导体部件，其中与偏移区的导电类型相反的导电类型的区域被并入漂移区以及活动区的区域中。

公开(公告)号：US06762455B2

公开(公告)日：2004-07-13

申请号：US10095270

申请日：2002-03-11

申请人： Klaus-Günter Oppermann ,  Jenö Tihanyi

发明人： Klaus-Günter Oppermann ,  Jenö Tihanyi

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766

摘要： A semiconductor component includes a semiconductor body of a first conductivity type which accommodates a space charge region. Semiconductor regions of a second conductivity type are disposed in at least one plane extending essentially perpendicularly to a connecting line extending between two electrodes. A cell array is disposed under one of the electrodes in the semiconductor body. At least some of the semiconductor regions of the second conductivity type are connected to the cell array via filiform semiconductor zones of the second conductivity type in order to expedite switching processes. A method for fabricating such a semiconductor component is also provided.

摘要翻译： 半导体部件包括容纳空间电荷区域的第一导电类型的半导体本体。 第二导电类型的半导体区域设置在基本上垂直于在两个电极之间延伸的连接线延伸的至少一个平面中。 电池阵列设置在半导体本体中的一个电极下方。 第二导电类型的至少一些半导体区域通过第二导电类型的丝状半导体区域连接到电池阵列，以便加速切换工艺。 还提供了制造这种半导体部件的方法。

公开(公告)号：US06646304B1

公开(公告)日：2003-11-11

申请号：US09688922

申请日：2000-10-16

申请人： Jenö Tihanyi ,  Reinhard Ploss

发明人： Jenö Tihanyi ,  Reinhard Ploss

IPC分类号： H01L2976

CPC分类号： H01L29/0634 ,  H01L21/187 ,  H01L21/22 ,  H01L21/261 ,  H01L21/26513 ,  H01L29/0623 ,  H01L29/167 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/6634 ,  H01L29/7396 ,  H01L29/744 ,  H01L29/7811 ,  H01L29/8613 ,  H01L2924/0002 ,  H01L2924/00

摘要： A universal semiconductor wafer for high-voltage semiconductor components includes at least one layer of a first conductivity type which is provided on a semiconductor substrate of the first conductivity type. A plurality of floating semiconductor zones of a second, opposite conductivity type are embedded in the interface region between the semiconductor substrate and the at least one layer. The floating semiconductor zones are dimensioned such that the dimension of a semiconductor zone is do small compared to the layer thickness of the at least one semiconductor layer and is essentially equal to or less than a distance between the floating semiconductor zones in the interface region.

摘要翻译： 用于高压半导体部件的通用半导体晶片包括设置在第一导电类型的半导体衬底上的至少一层第一导电类型。 具有第二相反导电类型的多个浮动半导体区域被嵌入在半导体衬底和至少一个层之间的界面区域中。 浮动半导体区的尺寸使得半导体区的尺寸比至少一个半导体层的层厚度小，并且基本上等于或小于界面区域中的浮动半导体区之间的距离。

公开(公告)号：US07375395B2

公开(公告)日：2008-05-20

申请号：US11233472

申请日：2005-09-22

申请人： Jenö Tihanyi

发明人： Jenö Tihanyi

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L29/7825 ,  H01L21/2257 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66696 ,  H01L29/66704

摘要： The invention relates to a vertical field-effect transistor in source-down structure, in which the active zones (10, 7, 11) are introduced from trenches (5, 8, 9) into a semiconductor body (1), a source electrode (18) being connected via the filling (6) of a body trench (5) to a highly doped substrate (2) via a conductive connection (15).

摘要翻译： 本发明涉及一种源 - 下结构中的垂直场效应晶体管，其中有源区（10,7,11）从沟槽（5,8,9）引入半导体本体（1），源电极 （18）经由导体连接（15）经由体沟槽（5）的填充物（6）连接到高度掺杂的衬底（2）。

公开(公告)号：US07038272B2

公开(公告)日：2006-05-02

申请号：US10631350

申请日：2003-07-31

申请人： Hans Weber ,  Dirk Ahlers ,  Uwe Wahl ,  Jenö Tihanyi ,  Armin Willmeroth

发明人： Hans Weber ,  Dirk Ahlers ,  Uwe Wahl ,  Jenö Tihanyi ,  Armin Willmeroth

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/7816

摘要： In a method for forming a channel zone in field-effect transistors, a polysilicon layer is patterned above the channel zone to be formed. The polysilicon layer serves as a mask substrate for the subsequent doping of the channel zone. The expedient patterning of the polysilicon layer with holes in a gate region and pillars in a source region enables the channel zone to be doped more lightly. In another embodiment, the novel method is used for a channel width shading of a PMOS transistor cell.

摘要翻译： 在场效应晶体管中形成沟道区的方法中，在要形成的沟道区之上形成多晶硅层。 多晶硅层用作用于随后掺杂沟道区的掩模基板。 在栅极区域中具有空穴的多晶硅层的有利图案化以及源极区域中的柱状物使得能够更容易地掺杂沟道区。 在另一个实施例中，新颖的方法用于PMOS晶体管单元的沟道宽度阴影。

公开(公告)号：US06847091B2

公开(公告)日：2005-01-25

申请号：US09756539

申请日：2001-01-08

申请人： Gerald Deboy ,  Heinz Mitlehner ,  Jenö Tihanyi

发明人： Gerald Deboy ,  Heinz Mitlehner ,  Jenö Tihanyi

IPC分类号： H01L29/744 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/12 ,  H01L29/24 ,  H01L29/78 ,  H01L29/80 ,  H01L23/58

CPC分类号： H01L29/7802 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/66068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical semiconductor component having a semiconductor body of a first conductivity type is described. In a surface region of the semiconductor body, at least one zone of a second conductivity type, opposite to the first conductivity type, is embedded. Regions of the second conductivity type are provided in the semiconductor body in a plane running substantially parallel to the surface of the surface region. The regions are in this case sufficiently highly doped that they cannot be depleted of charge carriers when a voltage is applied.

摘要翻译： 描述具有第一导电类型的半导体本体的垂直半导体部件。 在半导体本体的表面区域中嵌有与第一导电类型相反的至少一个第二导电类型的区域。 第二导电类型的区域在基本平行于表面区域的表面的平面中设置在半导体本体中。 在这种情况下，这些区域具有足够高的掺杂性，当施加电压时它们不能耗尽电荷载流子。

公开(公告)号：US06507071B1

公开(公告)日：2003-01-14

申请号：US09694435

申请日：2000-10-23

申请人： Jenö Tihanyi

发明人： Jenö Tihanyi

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7812 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/78624

摘要： A lateral high-voltage sidewall transistor configuration includes a low-doped semiconductor substrate of a first conductivity type and a low-doped epitaxial layer of a second conductivity type disposed on the semiconductor substrate. First semiconductor layers of the first conductivity type and second semiconductor layers of the second conductivity type are disposed in an alternating configuration in the epitaxial layer. A source region and a drain region of the second conductivity type extend through the first and second semiconductor layers as far as the semiconductor substrate. A gate electrode includes a gate insulating layer lining a gate trench and includes a conductive material which fills the gate trench. The gate electrode extends through the first and second semiconductor layers as far as the semiconductor substrate and is disposed adjacent to the source region toward the drain region. A semiconductor region of the first conductivity type is disposed on at least one side of the source region and the gate trench, the semiconductor region extending as far as the semiconductor substrate and extending under the source region and partially under the gate insulating layer.

摘要翻译： 横向高压侧壁晶体管配置包括设置在半导体衬底上的第一导电类型的低掺杂半导体衬底和第二导电类型的低掺杂外延层。 第一导电类型的第一半导体层和第二导电类型的第二半导体层以交替的形式设置在外延层中。 第二导电类型的源区和漏区延伸穿过第一和第二半导体层至半导体衬底。 栅电极包括衬在栅极沟槽上的栅极绝缘层，并且包括填充栅极沟槽的导电材料。 栅电极延伸穿过第一和第二半导体层直到半导体衬底并且被设置成与源极区域相邻地朝向漏极区域。 第一导电类型的半导体区域设置在源极区域和栅极沟槽的至少一侧上，半导体区域延伸到半导体衬底的深度并在源极区域下方并且部分地在栅极绝缘层下方延伸。

公开(公告)号：US07199403B2

公开(公告)日：2007-04-03

申请号：US10901634

申请日：2004-07-29

申请人： Jenö Tihanyi

发明人： Jenö Tihanyi

IPC分类号： H01L29/00

CPC分类号： H01L29/7813 ,  H01L29/866

摘要： The invention relates to a semiconductor arrangement having a MOSFET structure and an active zener function. A n+-doped zone and a p+-doped zone are provided at the bottom of a trench for the purpose of forming zener diodes, the n+-doped zone being directly connected to the gate electrode.

摘要翻译： 本发明涉及具有MOSFET结构和有源齐纳功能的半导体装置。 为了形成齐纳二极管的目的，在沟槽的底部设置有n + + + - 掺杂区和ap + + - 掺杂区，n + SUP-掺杂区直接连接到栅电极。

公开(公告)号：US06912153B2

公开(公告)日：2005-06-28

申请号：US10619125

申请日：2003-07-14

申请人： Jenö Tihanyi

发明人： Jenö Tihanyi

IPC分类号： G11C16/02 ,  H01L27/102 ,  H01L27/24 ,  G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/1021 ,  H01L27/24

摘要： A memory cell stores data permanently in a memory material that can assume a first, high-resistance state and a second, low-resistance state, that is in a phase-changeable or ovonic material. A heating device is disposed to heat the memory material at different rates to a programming temperature. The memory material either has a high resistance or a low resistance after cooling, depending on the heating rate. The heating device has a switching device and a heating element in immediate vicinity to the memory material. The switching device has a field-effect transistor and a drain region of the field-effect transistor forms the heating element. Alternatively, the heating element includes a diode or a diode chain.

摘要翻译： 存储单元将数据永久地存储在可以呈现第一高电阻状态和第二低电阻状态的存储器材料中，该第一高电阻状态和第二低电阻状态处于可相位变化或超声波材料中。 设置加热装置以将记忆材料以不同的速率加热到编程温度。 记忆材料在冷却后具有高电阻或低电阻，这取决于加热速率。 加热装置具有紧邻存储材料的开关装置和加热元件。 开关器件具有场效应晶体管，场效应晶体管的漏极区形成加热元件。 或者，加热元件包括二极管或二极管链。