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18 条记录 (耗时 0.017 秒)

    Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it
    3.
    发明授权
    Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it 有权
    具有电荷补偿结构和单片集成电路的半导体功率器件及其制造方法

    公开(公告)号：US07332788B2

    公开(公告)日：2008-02-19

    申请号：US10927270

    申请日：2004-08-26

    申请人： Dirk Ahlers ,  Miguel Cuadron Marion ,  Uwe Wahl ,  Armin Willmeroth

    发明人： Dirk Ahlers ,  Miguel Cuadron Marion ,  Uwe Wahl ,  Armin Willmeroth

    IPC分类号： H01L29/00

    CPC分类号： H01L29/7802 ,  H01L27/0883 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/66712

    摘要： The invention relates to a semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it. In the case of this semiconductor power device, zones (6) in charge compensation cells (27) that are arranged vertically and doped complimentarily to the semiconductor chip volume (5) are arranged in the entire chip volume, the complimentarily doped zones (6) extending right into surface regions (11) of the semiconductor power elements (7) and not projecting into surface regions (12) of semiconductor surface elements (1).

    摘要翻译： 本发明涉及具有电荷补偿结构和单片集成电路的半导体功率器件及其制造方法。 在该半导体功率器件的情况下，在芯片体积整体上配置垂直配置并与半导体芯片体积（5）相辅相成的电荷补偿单元（27）的区域（6），补充掺杂区域（6） 延伸到半导体功率元件（7）的表面区域（11）中，并且不突出到半导体表面元件（1）的表面区域（12）中。

    High-voltage semiconductor component
    5.
    发明授权
    High-voltage semiconductor component 有权
    高压半导体元件

    公开(公告)号：US06894329B2

    公开(公告)日：2005-05-17

    申请号：US10455839

    申请日：2003-06-06

    申请人： Gerald Deboy ,  Dirk Ahlers ,  Helmut Strack ,  Michael Rueb ,  Hans Martin Weber

    发明人： Gerald Deboy ,  Dirk Ahlers ,  Helmut Strack ,  Michael Rueb ,  Hans Martin Weber

    IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/80

    CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7825

    摘要： A semiconductor component has a semiconductor body comprising blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode. The side of the zone of the second conductivity type facing the drain zone forms a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, comprises areas of the first and second conductivity type nested in one another. The second surface coincides with the surface of the drain zone facing the source zone, such that the regions of the first and second conductivity type nested inside each other reach the drain zone.

    摘要翻译： 半导体部件具有包含阻挡pn结的半导体主体，与第一电极连接并与形成与第一导电类型互补的第二导电类型的阻挡pn结的区域接壤的第一导电类型的源极区和漏极 连接到第二电极的第一导电类型的区域。 面向排水区的第二导电类型的区域的一侧形成第一表面，并且在位于第一表面和漏区之间的第一表面和第二表面之间的区域中，包括第一和第二导电类型的区域 彼此嵌套在一起 第二表面与面向源区的排水区的表面重合，使得彼此嵌套的第一和第二导电类型的区域到达排水区。

    High-voltage semiconductor component
    6.
    发明授权
    High-voltage semiconductor component 有权
    高压半导体元件

    公开(公告)号：US06825514B2

    公开(公告)日：2004-11-30

    申请号：US10455858

    申请日：2003-06-06

    申请人： Gerald Deboy ,  Dirk Ahlers ,  Helmut Strack ,  Michael Rueb ,  Hans Martin Weber

    发明人： Gerald Deboy ,  Dirk Ahlers ,  Helmut Strack ,  Michael Rueb ,  Hans Martin Weber

    IPC分类号： H01L2980

    CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7801 ,  H01L29/7802

    摘要： A process for manufacturing of a semiconductor device comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode, the side of the zone of the second conductivity type facing the drain zone forming a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, areas of the first and second conductivity type nested in one another, comprises the step of: varying in individual semiconductor layers, by doping, the degree of compensation in the regions of the second conductivity type.

    摘要翻译： 一种用于制造半导体器件的方法，该半导体器件包括阻挡pn结，与第一电极连接并与形成与第一导电类型互补的第二导电类型的阻挡pn结的区域接壤的第一导电类型的源区，以及 连接到第二电极的第一导电类型的漏极区，形成第一表面的第二导电类型的区域的侧面，并且在第一表面和位于第一表面之间的第二表面之间的区域中 并且漏区，第一和第二导电类型的区域彼此嵌套，包括以下步骤：通过掺杂在各个半导体层中改变第二导电类型的区域中的补偿程度。

    Vertical high-voltage semiconductor component
    8.
    发明授权
    Vertical high-voltage semiconductor component 有权
    垂直高压半导体元件

    公开(公告)号：US06765262B2

    公开(公告)日：2004-07-20

    申请号：US10244789

    申请日：2002-09-16

    申请人： Dirk Ahlers ,  Wolfgang Werner

    发明人： Dirk Ahlers ,  Wolfgang Werner

    IPC分类号： H01L29772

    CPC分类号： H01L29/7801 ,  H01L29/0634 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/7802 ,  H01L29/8083

    摘要： The present invention relates to a high-voltage semiconductor component having a semiconductor substrate of a first conduction type on which a semiconductor layer is provided as a drift path that takes up the reverse voltage of the semiconductor component. The semiconductor layer is either of the first conduction type or of a second conduction type that is opposite the first conduction type. The semiconductor layer is more weakly doped than the semiconductor substrate. Laterally oriented semiconductor regions of the first and second conduction types are alternately provided in the semiconductor layer. Furthermore, the present invention relates to a high-voltage semiconductor component having a MOS field-effect transistor that is formed in a semiconductor substrate and has a drift path that is connected to its drain electrode.

    摘要翻译： 本发明涉及一种具有第一导电类型的半导体衬底的高电压半导体元件，其上设置半导体层作为占据半导体元件的反向电压的漂移路径。 半导体层是与第一导电类型相反的第一导电型或第二导电型。 半导体层比半导体衬底更弱掺杂。 在半导体层中交替地设置第一和第二导电类型的横向取向的半导体区域。 此外，本发明涉及具有MOS场效应晶体管的高电压半导体元件，该MOS场效应晶体管形成在半导体衬底中并具有连接到其漏电极的漂移路径。

    Method for forming a channel zone of a transistor and NMOS transistor
    9.
    发明授权
    Method for forming a channel zone of a transistor and NMOS transistor 失效
    用于形成晶体管和NMOS晶体管的沟道区的方法

    公开(公告)号：US07038272B2

    公开(公告)日：2006-05-02

    申请号：US10631350

    申请日：2003-07-31

    申请人： Hans Weber ,  Dirk Ahlers ,  Uwe Wahl ,  Jenö Tihanyi ,  Armin Willmeroth

    发明人： Hans Weber ,  Dirk Ahlers ,  Uwe Wahl ,  Jenö Tihanyi ,  Armin Willmeroth

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/7816

    摘要： In a method for forming a channel zone in field-effect transistors, a polysilicon layer is patterned above the channel zone to be formed. The polysilicon layer serves as a mask substrate for the subsequent doping of the channel zone. The expedient patterning of the polysilicon layer with holes in a gate region and pillars in a source region enables the channel zone to be doped more lightly. In another embodiment, the novel method is used for a channel width shading of a PMOS transistor cell.

    摘要翻译： 在场效应晶体管中形成沟道区的方法中，在要形成的沟道区之上形成多晶硅层。 多晶硅层用作用于随后掺杂沟道区的掩模基板。 在栅极区域中具有空穴的多晶硅层的有利图案化以及源极区域中的柱状物使得能够更容易地掺杂沟道区。 在另一个实施例中，新颖的方法用于PMOS晶体管单元的沟道宽度阴影。