利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.011 秒)

    Memory array using mechanical switch and method for operating thereof
    2.
    发明授权
    Memory array using mechanical switch and method for operating thereof 有权
    使用机械开关的存储器阵列及其操作方法

    公开(公告)号：US07787276B2

    公开(公告)日：2010-08-31

    申请号：US12122318

    申请日：2008-05-16

    申请人： Jun-Bo Yoon ,  Weon-Wi Jang ,  Jeong-Oen Lee

    发明人： Jun-Bo Yoon ,  Weon-Wi Jang ,  Jeong-Oen Lee

    IPC分类号： G11C5/00

    CPC分类号： G11C23/00 ,  G11C11/565

    摘要： A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word lines; a drain electrode spaced apart from the gate electrode and connected to a capacitor; and a source electrode comprises: an anchor part spaced apart from the gate electrode and connected to each of the bit lines; a mobile part where a dimple is formed, comprises the steps of: applying a first voltage V1 to the bit line selected from the plurality of bit lines; applying a second voltage V2 greater than a sum of the first voltage V1 and a pull-in voltage Vpi to the word lines selected from the plurality of word lines; and applying a voltage smaller than a sum of a erase voltage Verase and the pull-in voltage Vpi and a voltage greater than a difference between a write voltage Vwrite and the pull-in voltage Vpi to the word lines unselected from the plurality of word lines.

    摘要翻译： 一种使用根据本发明的机械开关来控制存储器阵列的方法，其中存储器阵列包括： 多个字线; 多个位线与所述多个字线相交; 连接到每个字线的栅电极; 与栅电极间隔开并连接到电容器的漏电极; 并且源电极包括：与栅电极间隔开并连接到每个位线的锚定部分; 形成凹坑的移动部件包括以下步骤：将第一电压V1施加到从多个位线中选择的位线; 将大于第一电压V1和引入电压Vpi的和的第二电压V2施加到从多个字线中选择的字线; 以及将小于擦除电压Verase和引入电压Vpi之和的电压和大于写入电压V write和引入电压Vpi之间的电压的电压施加到从多个字线未被选择的字线 。

    Method for fabricating large-area nanoscale pattern
    4.
    发明授权
    Method for fabricating large-area nanoscale pattern 有权
    制造大面积纳米尺度图案的方法

    公开(公告)号：US08956962B2

    公开(公告)日：2015-02-17

    申请号：US13242331

    申请日：2011-09-23

    申请人： Young-Jae Lee ,  Kyoung Jong Yoo ,  Jin Su Kim ,  Jun Lee ,  Yong In Lee ,  JunBo Yoon ,  JeongHo Yeon ,  Joo-Hyung Lee ,  Jeong Oen Lee

    发明人： Young-Jae Lee ,  Kyoung Jong Yoo ,  Jin Su Kim ,  Jun Lee ,  Yong In Lee ,  JunBo Yoon ,  JeongHo Yeon ,  Joo-Hyung Lee ,  Jeong Oen Lee

    IPC分类号： H01L21/40 ,  H01L21/033 ,  B82Y10/00

    CPC分类号： H01L21/0337 ,  B82Y10/00 ,  H01L21/0338 ,  Y10S438/947

    摘要： A method for fabricating a large-area nanoscale pattern includes: forming multilayer main thin films isolated by passivation layers; patterning a first main thin film to form a first main pattern; forming a first spacer pattern with respect to the first main pattern; and forming a second main pattern by transferring the first spacer pattern onto a second main thin film. By using multilayer main thin films isolated by different passivation films, spacer lithography capable of reducing a pattern pitch can be repetitively performed, and the pattern pitch is repetitively reduced without shape distortion after formation of micrometer-scale patterns, thereby forming nanometer-scale fine patterns uniformly over a wide area.

    摘要翻译： 一种制造大面积纳米级图案的方法包括：形成由钝化层隔离的多层主薄膜; 图案化第一主薄膜以形成第一主图案; 相对于所述第一主图形形成第一间隔图案; 以及通过将第一间隔图案转印到第二主薄膜上而形成第二主图案。 通过使用由不同钝化膜分离的多层主薄膜，可以重复地进行能够减小图案间距的间隔光刻，并且在形成微米尺度图案之后，图案间距重复减小而没有形状变形，从而形成纳米级精细图案 均匀地在广泛的地区。

    METHOD FOR FABRICATING LARGE-AREA NANOSCALE PATTERN
    5.
    发明申请
    METHOD FOR FABRICATING LARGE-AREA NANOSCALE PATTERN 有权
    用于制作大面积纳米图案的方法

    公开(公告)号：US20120156882A1

    公开(公告)日：2012-06-21

    申请号：US13242331

    申请日：2011-09-23

    申请人： YOUNG-JAE LEE ,  KYOUNG JONG YOO ,  JIN SU KIM ,  JUN LEE ,  YONG IN LEE ,  JUNBO YOON ,  JEONGHO YEON ,  JOO-HYUNG LEE ,  JEONG OEN LEE

    发明人： YOUNG-JAE LEE ,  KYOUNG JONG YOO ,  JIN SU KIM ,  JUN LEE ,  YONG IN LEE ,  JUNBO YOON ,  JEONGHO YEON ,  JOO-HYUNG LEE ,  JEONG OEN LEE

    IPC分类号： H01L21/308

    CPC分类号： H01L21/0337 ,  B82Y10/00 ,  H01L21/0338 ,  Y10S438/947

    摘要： A method for fabricating a large-area nanoscale pattern includes: forming multilayer main thin films isolated by passivation layers; patterning a first main thin film to form a first main pattern; forming a first spacer pattern with respect to the first main pattern; and forming a second main pattern by transferring the first spacer pattern onto a second main thin film. By using multilayer main thin films isolated by different passivation films, spacer lithography capable of reducing a pattern pitch can be repetitively performed, and the pattern pitch is repetitively reduced without shape distortion after formation of micrometer-scale patterns, thereby forming nanometer-scale fine patterns uniformly over a wide area.

    摘要翻译： 一种制造大面积纳米级图案的方法包括：形成由钝化层隔离的多层主薄膜; 图案化第一主薄膜以形成第一主图案; 相对于所述第一主图形形成第一间隔图案; 以及通过将第一间隔图案转印到第二主薄膜上而形成第二主图案。 通过使用由不同钝化膜分离的多层主薄膜，可以重复地进行能够减小图案间距的间隔光刻，并且在形成微米尺度图案之后，图案间距重复减小而没有形状变形，从而形成纳米级精细图案 均匀地在广泛的地区。

    MEMORY ARRAY USING MECHANICAL SWITCH AND METHOD FOR OPERATING THEREOF
    7.
    发明申请
    MEMORY ARRAY USING MECHANICAL SWITCH AND METHOD FOR OPERATING THEREOF 有权
    使用机械开关的存储器阵列及其操作方法

    公开(公告)号：US20090021972A1

    公开(公告)日：2009-01-22

    申请号：US12122318

    申请日：2008-05-16

    申请人： Jun-Bo Yoon ,  Jeong-Oen Lee ,  Weon-Wi Jang

    发明人： Jun-Bo Yoon ,  Jeong-Oen Lee ,  Weon-Wi Jang

    IPC分类号： G11C5/00 ,  G11C11/24 ,  G11C7/00

    CPC分类号： G11C23/00 ,  G11C11/565

    摘要： A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word lines; a drain electrode spaced apart from the gate electrode and connected to a capacitor; and a source electrode comprises: an anchor part spaced apart from the gate electrode and connected to each of the bit lines; a mobile part where a dimple is formed, comprises the steps of: applying a first voltage V1 to the bit line selected from the plurality of bit lines; applying a second voltage V2 greater than a sum of the first voltage V1 and a pull-in voltage Vpi to the word lines selected from the plurality of word lines; and applying a voltage smaller than a sum of a erase voltage Verase and the pull-in voltage Vpi and a voltage greater than a difference between a write voltage Vwrite and the pull-in voltage Vpi to the word lines unselected from the plurality of word lines.

    摘要翻译： 一种使用根据本发明的机械开关来控制存储器阵列的方法，其中存储器阵列包括： 多个字线; 多个位线与所述多个字线相交; 连接到每个字线的栅电极; 与栅电极间隔开并连接到电容器的漏电极; 并且源电极包括：与栅电极间隔开并连接到每个位线的锚定部分; 形成凹坑的移动部件包括以下步骤：将第一电压V1施加到从多个位线中选择的位线; 将大于第一电压V1和引入电压Vpi的和的第二电压V2施加到从多个字线中选择的字线; 以及将小于擦除电压Verase和引入电压Vpi之和的电压和大于写入电压V write和引入电压Vpi之间的电压的电压施加到从多个字线未被选择的字线 。