公开(公告)号：US06525589B1

公开(公告)日：2003-02-25

申请号：US09695705

申请日：2000-10-25

申请人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Aryesh Amar ,  Jerome E. Johnston

发明人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Aryesh Amar ,  Jerome E. Johnston

IPC分类号： H03K1716

CPC分类号： H03M3/494 ,  G01D3/022 ,  H03M3/448 ,  H03M3/452

摘要： An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.

摘要翻译： 仪表电路具有具有输入端子的集成电路，使用前馈补偿的放大器装置和模数转换器以及接收来自所述放大器装置的输出的串行数据输出。 具有换能器或热电偶布置的桥式电路连接到集成电路的输入端子。

公开(公告)号：US06857002B1

公开(公告)日：2005-02-15

申请号：US09695704

申请日：2000-10-25

申请人： Axel Thomsen ,  Jerome E. Johnston ,  Edwin De Angel ,  Aryesh Amar

发明人： Axel Thomsen ,  Jerome E. Johnston ,  Edwin De Angel ,  Aryesh Amar

IPC分类号： G06F13/00 ,  G06F17/10 ,  H03H17/02 ,  H03M3/02

CPC分类号： H03H17/0294 ,  H03M3/392 ,  H03M3/462

摘要： In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

摘要翻译： 在具有模拟数字转换器的信号处理集成电路和具有时间分离的多个抽头的数字滤波器的情况下，当在复位或输入通道改变之后开始转换时，滤波器将具有不完整的输入数据集 输出计算的延迟输入从复位操作全部为零。 在复位之后，在数据填满过滤器管线的时间期间，输出值的计算将给出保存有关输入信息的结果，但不显示具有与完全设置的过滤器相同的缩放和频率内容的数据 。 集成电路有选择地提供两种模式，其中仅提供来自滤波器的完全确定的数据，或者提供来自滤波器的所有数据的另一种模式，包括不稳定的数据。 关于滤波器系数的知识可以由用户或用户进程利用来从未解决的数据中提取关于输入的信息。

公开(公告)号：US06891430B1

公开(公告)日：2005-05-10

申请号：US09695706

申请日：2000-10-25

申请人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Lei Wang ,  Aryesh Amar

发明人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Lei Wang ,  Aryesh Amar

IPC分类号： H03M3/00 ,  G06G7/12

CPC分类号： H03M3/494 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

摘要： A signal processing integrated circuit has having a chopper stabilized, multistage, feedforward amplifier and a delta sigma analog to digital converter. Filtering of the output of the output from the analog to digital converter comprises a sinc5 filter and a sinc3 filter. The sinc3 filter may be bypassed. A rough buffer permits quick charging of a sample and hold capacitor during part of the charge cycle and slower but more accurate charging during the remainder of the charge cycle.

摘要翻译： 信号处理集成电路具有斩波稳定的多级前馈放大器和ΔΣ模数转换器。 从模数转换器输出的输出的滤波包括​​一个Sinc＆lt; 5＆gt;滤波器和一个sinc＆lt; 3＆gt; 3滤波器。 可以绕过sinc <3> 3滤波器。 一个粗略的缓冲器允许在充电周期的一部分期间快速充电一个采样和保持电容器，并且在充电周期的剩余时间内可以进行更慢但更精确的充电。

公开(公告)号：US07162506B1

公开(公告)日：2007-01-09

申请号：US11057450

申请日：2005-02-14

申请人： Axel Thomsen ,  Jerome E Johnston ,  Edwin Angel ,  Aryesh Amar

发明人： Axel Thomsen ,  Jerome E Johnston ,  Edwin Angel ,  Aryesh Amar

IPC分类号： G06F17/10

CPC分类号： H03H17/0294 ,  H03M3/392 ,  H03M3/462

摘要： In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

摘要翻译： 在具有模拟数字转换器的信号处理集成电路和具有时间分离的多个抽头的数字滤波器的情况下，当在复位或输入通道改变之后开始转换时，滤波器将具有不完整的输入数据集 输出计算的延迟输入从复位操作全部为零。 在复位之后，在数据填满过滤器管线的时间期间，输出值的计算将给出保存有关输入信息的结果，但不显示具有与完全设置的过滤器相同的缩放和频率内容的数据 。 集成电路有选择地提供两种模式，其中仅提供来自滤波器的完全确定的数据，或者提供来自滤波器的所有数据的另一种模式，包括不稳定的数据。 关于滤波器系数的知识可以由用户或用户进程利用来从未解决的数据中提取关于输入的信息。

公开(公告)号：US06426713B1

公开(公告)日：2002-07-30

申请号：US09695708

申请日：2000-10-25

申请人： Aryesh Amar ,  Edwin De Angel ,  Eric J. Swanson

发明人： Aryesh Amar ,  Edwin De Angel ,  Eric J. Swanson

IPC分类号： H03M106

CPC分类号： H03M1/1028 ,  H03M1/1225 ,  H03M3/38 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452 ,  H03M3/494

摘要： In a signal processing integrated circuit having a plurality of physical channels and a plurality of gain registers, a plurality of offset registers and an plurality of setup registers, mechanisms are provided to assign one of a plurality of gain registers independently of a selected one of a plurality of offset registers when processing signals from a physical channel.

摘要翻译： 在具有多个物理信道和多个增益寄存器的信号处理集成电路中，提供多个偏移寄存器和多个建立寄存器机制，以分配多个增益寄存器中的一个独立于所选择的一个 当处理来自物理信道的信号时，多个偏移寄存器。

公开(公告)号：US06469650B2

公开(公告)日：2002-10-22

申请号：US09800604

申请日：2001-03-06

申请人： Kartik Nanda ,  Aryesh Amar ,  Saibun Wong ,  Jerome E. Johnston

发明人： Kartik Nanda ,  Aryesh Amar ,  Saibun Wong ,  Jerome E. Johnston

IPC分类号： H03M112

CPC分类号： H03M3/392 ,  H03M3/474

摘要： A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.

摘要翻译： 公开了一种用于在确保完全稳定的转换输出和输入信号的连续转换的单个转换之间选择滤波器控制器的实现的方法和系统。 状态机确定转换开始信号是否具有持续时间，其结束于在输入信号上完成的转换的第一次出现之后或之前。 完成的转换是当从输入信号转换位设置时的出现。 如果转换开始信号具有在第一次完成转换之前或之前结束的持续时间，则状态机选择并实现输入信号的单次转换。 数字系统通过等待滤波器接收和过滤用于转换输出的预定数量的位组，然后输出转换输出，确保完全转换的输出。 否则，状态机选择并实现输入信号的连续转换。

公开(公告)号：US07348813B1

公开(公告)日：2008-03-25

申请号：US11292523

申请日：2005-12-02

申请人： Kartik Nanda ,  Aryesh Amar ,  Rahul Singh ,  Jerome E Johnston

发明人： Kartik Nanda ,  Aryesh Amar ,  Rahul Singh ,  Jerome E Johnston

IPC分类号： H03L7/00

CPC分类号： H03K19/0175 ,  H03K19/01

摘要： A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.

摘要翻译： 在不同电压域中操作的电路接口的方法包括：接收具有在第一电压域中工作的第一电路的第一信号，并产生具有在第二电压域中工作的第二电路的第二信号。 第二信号在电平移位器之间在第一和第二电压域之间电平移位，并且与第一信号同步，第三电路在第一电压域中工作。

公开(公告)号：US06522274B1

公开(公告)日：2003-02-18

申请号：US09321583

申请日：1999-05-28

申请人： Aryesh Amar ,  Jerome E. Johnston ,  Donald Keith Coffey

发明人： Aryesh Amar ,  Jerome E. Johnston ,  Donald Keith Coffey

IPC分类号： H03M112

CPC分类号： G06F3/05 ,  H03M1/1225

摘要： A method and apparatus are used to process a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information. Command bits are set over a serial port input pin, and include at least one pointer bit indicative of a selected logical channel. In response to the command bits, the serial port controller sends signals indicative of the physical channel and the converter property specified in the selected logical channel to the ADC components.

摘要翻译： 一种方法和装置用于使用具有模数转换器（ADC）组件的电路，串行端口接口和串行端口控制器在相应的多个物理信道上处理多个模拟信号。 一个或多个逻辑信道的逻辑信道信息存储在串行端口控制器的寄存器中。 每个逻辑信道指定一个物理信道和转换信息。 命令位通过串行端口输入引脚设置，并且包括指示所选逻辑通道的至少一个指针位。 响应于命令位，串行端口控制器将指示所选逻辑信道中指定的物理信道和转换器特性的信号发送到ADC组件。

公开(公告)号：US5886658A

公开(公告)日：1999-03-23

申请号：US856558

申请日：1997-05-15

申请人： Aryesh Amar ,  Jerome E. Johnston ,  Bruce P. Del Signore

发明人： Aryesh Amar ,  Jerome E. Johnston ,  Bruce P. Del Signore

IPC分类号： G06F3/05 ,  H03M1/00

CPC分类号： G06F3/05

摘要： A novel serial port interface system and method are disclosed. The serial port interface system achieves a three-pin interface mode with only a serial data input pin, a serial data output pin, and a serial clock pin by allocating a bit in an on-chip register to identify a three-pin conversion-done mode. In this three-pin mode, the serial data output pin signals an external device that data is ready to be accessed. Also disclosed with this three-pin conversion-done mode is a single conversion data read and a continuous conversion data read that may be selected through two separate bits in an on-chip register. In another aspect, a multiple register access capability is disclosed that allows multiple on-chip registers to be accessed with a single read/write command. This is accomplished by allocating a register select address in a command register to identify a group of registers, such as all of the set-up registers (gain, offset and configuration). An invalid command lock mode is also disclosed that places the serial port interface in a hold state, if an invalid command is decoded, to protect on-chip registers from corruption. Control of the serial port interface is removed from an external device until a specific restart sequence is applied.

摘要翻译： 公开了一种新颖的串口接口系统和方法。 串行端口接口系统通过在片内寄存器中分配一个位来实现三针接口模式，只需一个串行数据输入引脚，串行数据输出引脚和串行时钟引脚，以识别三引脚转换完成 模式。 在这种三引脚模式下，串行数据输出引脚将信号通知外部设备，数据准备就绪。 还公开了这种三引脚转换完成模式是单片转换数据读取和连续转换数据读取，其可以通过片上寄存器中的两个分开的位来选择。 在另一方面，公开了一种多寄存器访问能力，其允许通过单个读/写命令访问多个片上寄存器。 这是通过在命令寄存器中分配寄存器选择地址来识别一组寄存器，例如所有的建立寄存器（增益，偏移和配置）来实现的。 还公开了无效的命令锁定模式，如果无效命令被解码，则将串行端口接口置于保持状态，以保护片上寄存器免受损坏。 串行端口接口的控制从外部设备中删除，直到应用特定的重新启动顺序为止。

公开(公告)号：US06642879B2

公开(公告)日：2003-11-04

申请号：US09906916

申请日：2001-07-16

申请人： Aryesh Amar ,  Philip Steiner

发明人： Aryesh Amar ,  Philip Steiner

IPC分类号： H03M112

CPC分类号： H03M3/32 ,  H03M1/002 ,  H03M3/474

摘要： A method and system for powering down an analog-to-digital converter (“ADC”) into a sleep mode are disclosed. If the ADC receives a normal set of pulses for a serial clock signal of the ADC, a serial interface controller outputs converted data requested by a user through a serial interface. Also, if the ADC receives a sleep set of pulses for the serial clock signal, a state machine of the ADC powers down the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level. Furthermore, if the ADC is in the sleep mode and the ADC receives a wake-up set of pulses for the serial clock signal, the state machine powers back up the ADC from the sleep mode.

摘要翻译： 公开了一种将模拟 - 数字转换器（“ADC”）掉电进入休眠模式的方法和系统。 如果ADC接收到ADC的串行时钟信号的正常脉冲组，则串行接口控制器通过串行接口输出用户请求的转换数据。 此外，如果ADC接收到串行时钟信号的睡眠脉冲组，则ADC的状态机将ADC降频到睡眠模式，其中ADC的至少部分以降低的功耗水平运行。 此外，如果ADC处于睡眠模式，并且ADC接收到串行时钟信号的唤醒脉冲组，则状态机将从睡眠模式备份ADC。