公开(公告)号：US5264328A

公开(公告)日：1993-11-23

申请号：US874286

申请日：1992-04-24

申请人： Ronald A. DellaGuardia ,  John L. Mauer, IV ,  David E. Seeger

发明人： Ronald A. DellaGuardia ,  John L. Mauer, IV ,  David E. Seeger

IPC分类号： G03F7/26 ,  G03F7/30 ,  H01L21/027 ,  H01L21/30 ,  H01L21/66 ,  G03C5/02

CPC分类号： G03F7/30 ,  Y10S430/168

摘要： The present invention provides a method for determining the development endpoint in a X-ray lithographic process. Endpoint is determined by visually observing resist test field patterns through a microscope during the developing step. During the developing, changing test field patterns are formed because test field locations each had been exposed simultaneously to different radiation doses. These different doses are produced when radiation passes through a mask containing a plurality of different size radiation attenuators. When the changing test field pattern matches a known pattern, which is correlated to the desired development endpoint, the workpiece is removed from the developing step.

摘要翻译： 本发明提供了一种用于确定X射线光刻工艺中的显影终点的方法。 通过在显影步骤期间通过显微镜在视觉上观察抗蚀剂测试场图案来确定端点。 在开发期间，形成变化的测试场模式，因为测试场位置各自同时暴露于不同的辐射剂量。 当辐射通过包含多个不同尺寸的辐射衰减器的掩模时，产生这些不同的剂量。 当改变的测试场模式匹配与期望的开发端点相关联的已知模式时，工件从显影步骤中移除。

公开(公告)号：US4691435A

公开(公告)日：1987-09-08

申请号：US263227

申请日：1981-05-13

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

IPC分类号： H01L29/47 ,  H01L29/872 ,  H01L21/385

CPC分类号： H01L29/872

摘要： A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

摘要翻译： 公开了用于在肖特基势垒二极管中制造小面积自对准保护环的方法。 垂直壁孔通过硅衬底上的电介质层完全各向异性地蚀刻。 掺杂多晶硅层沉积在有孔介电层上。 多晶硅被反射离子蚀刻掉，仅留下围绕电介质层中孔周边的衬里。 该结构被加热以将掺杂剂从衬里扩散到衬底中。 肖特基二极管金属沉积在通过介电层中的衬里孔暴露的衬底上。

公开(公告)号：US4454647A

公开(公告)日：1984-06-19

申请号：US296933

申请日：1981-08-27

申请人： Richard C. Joy ,  Bernard M. Kemlage ,  John L. Mauer, IV

发明人： Richard C. Joy ,  Bernard M. Kemlage ,  John L. Mauer, IV

IPC分类号： H01L21/822 ,  H01L21/302 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L23/52 ,  H01L27/04 ,  H01L29/73

CPC分类号： H01L21/763 ,  H01L21/743 ,  H01L21/76202

摘要： An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

摘要翻译： 描述了具有形成为隔离结构的一部分的衬底触点的集成电路结构和形成这种结构的方法。 集成电路结构由单体硅体构成，其具有围绕体内单晶硅的区域的介电隔离图案。 电介质隔离图案包括位于集成电路的表面的正下方的凹入电介质部分和延伸穿过凹入的电介质部分并且比凹部更进一步延伸到单晶硅体的深部分。 高度掺杂的多晶硅衬底触点位于隔离图案的深部内。 衬底接触从隔离图案的表面向下延伸到绝缘深部的底部，其中触点电连接到硅体。 各种集成电路器件结构中的任何一种可以并入单晶硅区域内。 这些器件包括双极晶体管，场效应晶体管，电容器，二极管，电阻器等。

公开(公告)号：US4454646A

公开(公告)日：1984-06-19

申请号：US296929

申请日：1981-08-27

申请人： Richard C. Joy ,  Bernard M. Kemlage ,  John L. Mauer, IV

发明人： Richard C. Joy ,  Bernard M. Kemlage ,  John L. Mauer, IV

IPC分类号： H01L21/76 ,  H01L21/31 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/822 ,  H01L27/04 ,  H01L29/73

CPC分类号： H01L21/76202 ,  H01L21/743 ,  H01L21/763

摘要： An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. At certain locations the deep portion of the pattern extends to the surface of the silicon body where interconnection metallurgy can electrically contact the polycrystalline silicon so as to form a substrate contact to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

摘要翻译： 描述了具有形成为隔离结构的一部分的衬底触点的集成电路结构及其制造方法。 集成电路结构由单体硅体构成，其具有围绕体内单晶硅的区域的介电隔离图案。 电介质隔离图案包括位于集成电路表面的正下方的凹入电介质部分，以及从凹陷电介质部分的与所述主体表面处的部分相反的侧面延伸到单晶硅体的深部分。 高度掺杂的多晶硅衬底触点位于隔离图案的深部内。 在某些位置处，图案的深部延伸到硅体的表面，其中互连冶金可以电接触多晶硅，以便形成与绝缘深部的底部的基板接触，其中触点电连接到 硅体。 各种集成电路器件结构中的任何一种可以并入单晶硅区域内。 这些器件包括双极晶体管，场效应晶体管，电容器，二极管，电阻器等。

公开(公告)号：US4367119A

公开(公告)日：1983-01-04

申请号：US179145

申请日：1980-08-18

申请人： Joseph S. Logan ,  John L. Mauer, IV ,  Laura B. Rothman ,  Geraldine C. Schwartz ,  Charles L. Standley

发明人： Joseph S. Logan ,  John L. Mauer, IV ,  Laura B. Rothman ,  Geraldine C. Schwartz ,  Charles L. Standley

IPC分类号： H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06 ,  C23F1/02

CPC分类号： H01L23/5226 ,  H01L21/4846 ,  H01L21/7688 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S438/951

摘要： Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.

摘要翻译： 使用双重复合掩模用于剥离多层结构工艺，其中基底组分层用作用于上覆层的反应离子蚀刻的蚀刻停止层。

公开(公告)号：US4222792A

公开(公告)日：1980-09-16

申请号：US73593

申请日：1979-09-10

申请人： Reginald F. Lever ,  John L. Mauer, IV ,  Alwin E. Michel ,  Laura B. Rothman

发明人： Reginald F. Lever ,  John L. Mauer, IV ,  Alwin E. Michel ,  Laura B. Rothman

IPC分类号： H01L21/76 ,  H01L21/31 ,  H01L21/312 ,  H01L21/316 ,  H01L21/762 ,  H01L21/26

CPC分类号： H01L21/316 ,  H01L21/3121 ,  H01L21/76229 ,  Y10S148/131

摘要： A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate, said process comprising the steps:(a) forming deep wide trenches in the planar surface of the silicon substrate;(b) forming a thin layer of silicon dioxide on the planar surface of the silicon substrate and the exposed silicon surfaces of said deep wide trenches;(c) applying resin glass (polysiloxane) to the planar surface of said semiconductor substrate and within said deep wide trenches;(d) spinning off at least a portion of the resin glass on the planar surface of the substrate;(e) baking the substrate at a low temperature;(f) exposing the resin glass contained within the deep wide trenches of substrate to the energy of an E-beam;(g) developing the resin glass contained on said substrate in a solvent;(h) heating said substrate in oxygen to convert said resin glass contained within said deep wide trenches to silicon dioxide;(i) depositing a layer of silicon dioxide to provide a planar silicon dioxide surface on the exposed the surface of said substrate; and(j) planarize exposed silicon dioxide surface to silicon of substrate.A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate as recited in the preceding paragraph, wherein the following steps are performed in lieu of step i of claim 1, said steps comprising:(i-1) apply a second thin layer of resin glass; and(i-2) convert said resin glass to silicon dioxide.

摘要翻译： 一种用于在硅半导体衬底的平面表面中提供深宽二氧化硅填充沟槽的平面深氧化物隔离工艺，所述方法包括以下步骤：（a）在硅衬底的平面表面中形成深宽沟槽; （b）在硅衬底的平面表面和所述深宽沟槽的暴露的硅表面上形成二氧化硅薄层; （c）将树脂玻璃（聚硅氧烷）施加到所述深宽沟槽的所述半导体衬底的平面上; （d）在所述基板的平面上剥离所述树脂玻璃的至少一部分; （e）在低温下烘烤该基材; （f）将包含在基底的深宽沟槽内的树脂玻璃暴露于电子束的能量; （g）在溶剂中显影所述基板上所含的树脂玻璃; （h）在氧气中加热所述衬底以将包含在所述深宽沟槽内的所述树脂玻璃转化为二氧化硅; （i）沉积二氧化硅层以在所述衬底的暴露的表面上提供平面二氧化硅表面; 和（j）将暴露的二氧化硅表面平坦化到衬底的硅。 一种用于在前述段落中提供的硅半导体衬底的平坦表面中提供深宽二氧化硅填充沟槽的平面深氧化物隔离工艺，其中执行以下步骤代替权利要求1的步骤i，所述步骤包括：（ i-1）涂一层树脂玻璃; 和（i-2）将所述树脂玻璃转化为二氧化硅。

公开(公告)号：US4688069A

公开(公告)日：1987-08-18

申请号：US806060

申请日：1985-12-06

申请人： Richard C. Joy ,  Bernard M. Kemlage ,  John L. Mauer, IV

发明人： Richard C. Joy ,  Bernard M. Kemlage ,  John L. Mauer, IV

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L29/72

CPC分类号： H01L21/76202 ,  H01L21/763

摘要： An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

摘要翻译： 描述了具有形成为隔离结构的一部分的衬底触点的集成电路结构和形成这种结构的方法。 集成电路结构由单体硅体构成，其具有围绕体内单晶硅的区域的介电隔离图案。 电介质隔离图案包括位于集成电路的表面的正下方的凹入电介质部分和延伸穿过凹入的电介质部分并且比凹部更进一步延伸到单晶硅体的深部分。 高度掺杂的多晶硅衬底触点位于隔离图案的深部内。 衬底接触从隔离图案的表面向下延伸到绝缘深部的底部，其中触点电连接到硅体。 各种集成电路器件结构中的任何一种可以并入单晶硅区域内。 这些器件包括双极晶体管，场效应晶体管，电容器，二极管，电阻器等。

公开(公告)号：US4796069A

公开(公告)日：1989-01-03

申请号：US63345

申请日：1987-06-18

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

IPC分类号： H01L29/872 ,  H01L29/48 ,  H01L29/04 ,  H01L29/34

CPC分类号： H01L29/872

摘要： A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

摘要翻译： 公开了用于在肖特基势垒二极管中制造小面积自对准保护环的方法。 垂直壁孔通过硅衬底上的电介质层完全各向异性地蚀刻。 掺杂多晶硅层沉积在有孔介电层上。 多晶硅被反射离子蚀刻掉，仅留下围绕电介质层中孔周边的衬里。 该结构被加热以将掺杂剂从衬里扩散到衬底中。 肖特基二极管金属沉积在通过介电层中的衬里孔暴露的衬底上。

公开(公告)号：US4494004A

公开(公告)日：1985-01-15

申请号：US510385

申请日：1983-07-01

申请人： John L. Mauer, IV ,  Michel S. Michail ,  Ollie C. Woodard

发明人： John L. Mauer, IV ,  Michel S. Michail ,  Ollie C. Woodard

IPC分类号： H01J37/147 ,  H01J37/317 ,  H01J37/302

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  H01J37/1474 ,  H01J37/3174 ,  H01J2237/30488 ,  H01J2237/30494 ,  H01J2237/31764

摘要： An electron beam method and apparatus, for writing patterns, such as on semiconductor wafers, in which the writing field is divided into a large number of overlapping subfields with a predetermined periodicity. Subfield to subfield moves are made in a stepped sequential scan, such as raster, while patterns, within a subfield, are addressed using vector scan and written using a sequential scan. Significant improvement in throughput results by the use of this electron beam method and apparatus which preferably employs magnetic deflection for the sequential scanning the subfields and electric deflection for vector scanning within the subfield.

摘要翻译： 一种电子束方法和装置，用于写入诸如半导体晶片的图案，其中写入场被划分成具有预定周期的大量重叠子场。 子场到子场移动是以阶梯式顺序扫描（例如光栅）进行的，而子场内的图案使用向量扫描寻址并使用顺序扫描进行写入。 通过使用该电子束方法和优选采用磁偏转进行顺序扫描子场的装置和在子场内的矢量扫描的电偏转的装置，可以显着提高吞吐量。

公开(公告)号：US4447824A

公开(公告)日：1984-05-08

申请号：US416437

申请日：1982-09-10

申请人： Joseph S. Logan ,  John L. Mauer, IV ,  Laura B. Rothman ,  Geraldine C. Schwartz ,  Charles L. Standley

发明人： Joseph S. Logan ,  John L. Mauer, IV ,  Laura B. Rothman ,  Geraldine C. Schwartz ,  Charles L. Standley

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L29/34 ,  H01L29/44 ,  H01L29/52

CPC分类号： H01L21/7688 ,  H01L21/4846 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/09701

摘要： Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.

摘要翻译： 使用双重复合掩模用于剥离多层结构工艺，其中基底组分层用作用于上覆层的反应离子蚀刻的蚀刻停止层。