公开(公告)号：US4691435A

公开(公告)日：1987-09-08

申请号：US263227

申请日：1981-05-13

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

IPC分类号： H01L29/47 ,  H01L29/872 ,  H01L21/385

CPC分类号： H01L29/872

摘要： A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

摘要翻译： 公开了用于在肖特基势垒二极管中制造小面积自对准保护环的方法。 垂直壁孔通过硅衬底上的电介质层完全各向异性地蚀刻。 掺杂多晶硅层沉积在有孔介电层上。 多晶硅被反射离子蚀刻掉，仅留下围绕电介质层中孔周边的衬里。 该结构被加热以将掺杂剂从衬里扩散到衬底中。 肖特基二极管金属沉积在通过介电层中的衬里孔暴露的衬底上。

公开(公告)号：US4796069A

公开(公告)日：1989-01-03

申请号：US63345

申请日：1987-06-18

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

IPC分类号： H01L29/872 ,  H01L29/48 ,  H01L29/04 ,  H01L29/34

CPC分类号： H01L29/872

摘要： A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

摘要翻译： 公开了用于在肖特基势垒二极管中制造小面积自对准保护环的方法。 垂直壁孔通过硅衬底上的电介质层完全各向异性地蚀刻。 掺杂多晶硅层沉积在有孔介电层上。 多晶硅被反射离子蚀刻掉，仅留下围绕电介质层中孔周边的衬里。 该结构被加热以将掺杂剂从衬里扩散到衬底中。 肖特基二极管金属沉积在通过介电层中的衬里孔暴露的衬底上。

公开(公告)号：US4427989A

公开(公告)日：1984-01-24

申请号：US293546

申请日：1981-08-14

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  James L. Walsh

IPC分类号： G11C11/41 ,  G11C11/34 ,  G11C11/401 ,  H01L21/8229 ,  H01L27/102 ,  H01L27/115 ,  H01L29/74

CPC分类号： H01L27/1023 ,  G11C11/34 ,  H01L27/1028 ,  H01L27/115

摘要： A dynamic memory cell has a P+ injector region surrounded by an N+ region in an N- layer on an N+ layer. The injector region is placed between N+ source and drain regions. Holes injected into the N-layer are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.

摘要翻译： 动态存储单元具有由N +层上的N层中的N +区包围的P +注入区。 喷射器区域放置在N +源极和漏极区域之间。 注入N层的孔被N +，N-界面处的高低接头捕获，并通过感测源极 - 漏极电流来检测。 当前级别用于在单元格中建立二进制一和零级。 对齐程序中的四个掩模简化了制造。

公开(公告)号：US4196440A

公开(公告)日：1980-04-01

申请号：US909338

申请日：1978-05-25

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  Hans B. Pogge

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  Hans B. Pogge

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/08 ,  H01L29/735 ,  H01L29/06

CPC分类号： H01L27/0821 ,  H01L21/76232 ,  H01L29/735 ,  Y10S148/031 ,  Y10S148/051 ,  Y10S148/085

摘要： Lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region are described. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages.

摘要翻译： 描述了分离的单晶硅袋中的侧向PNP或NPN器件，其中二氧化硅隔离围绕该口袋并且部分地在该表面之下在隔离的单晶区域内。 P发射体或N发射体扩散在部分延伸到单晶隔离袋中的二氧化硅部分上进行。 这种结构减少了垂直电流注入，即使在低的基极 - 发射极电压下也将提供相对较高的（β）增益。

公开(公告)号：US4510676A

公开(公告)日：1985-04-16

申请号：US558740

申请日：1983-12-06

申请人： Narasipur G. Anantha ,  Santosh P. Gaur ,  Yi-Shiou Huang ,  Paul J. Tsang

发明人： Narasipur G. Anantha ,  Santosh P. Gaur ,  Yi-Shiou Huang ,  Paul J. Tsang

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8224 ,  H01L29/08 ,  H01L29/735 ,  H01L21/265

CPC分类号： H01L29/6625 ,  H01L21/8224 ,  H01L29/0826 ,  H01L29/735

摘要： A method for making a lateral PNP transistor simultaneously with an NPN transistor and the resultant device wherein a first mask defines a base-width by the resistor implant for a P-type resistor and a second mask is overlaid asymmetrically on said first mask to partially cover the collector. At the same time that the NPN extrinsic base contact is made, P-type dopants are introduced in the areas exposed by the first and second masks to provide an emitter and a collector contact for the PNP transistor.

摘要翻译： 一种用于与NPN晶体管同时制造横向PNP晶体管的方法，其中第一掩模通过用于P型电阻器的电阻器注入限定基极宽度，并且第二掩模在所述第一掩模上非对称地覆盖以部分覆盖 收藏者。 在制造NPN外部基极接触的同时，P型掺杂剂被引入由第一和第二掩模暴露的区域中，以为PNP晶体管提供发射极和集电极触点。

公开(公告)号：US4535531A

公开(公告)日：1985-08-20

申请号：US360730

申请日：1982-03-22

申请人： Harsaran S. Bhatia ,  Jack A. Dorler ,  Santosh P. Gaur ,  John S. Lechaton ,  Joseph M. Mosley ,  Gurumakonda R. Srinivasan

发明人： Harsaran S. Bhatia ,  Jack A. Dorler ,  Santosh P. Gaur ,  John S. Lechaton ,  Joseph M. Mosley ,  Gurumakonda R. Srinivasan

IPC分类号： H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/082 ,  H01L29/10 ,  H01L21/82

CPC分类号： H01L27/0825 ,  H01L21/3065 ,  H01L21/8222 ,  H01L29/1004

摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization.

摘要翻译： 描述了一种方法，其允许在集成电路芯片的选定区域中制造非常窄的基极宽度双极晶体管，并且在同一集成电路芯片的其它选定区域上制造宽基极宽度的双极晶体管。 将晶体管特性从集成电路芯片的一个区域选择性地变化到另一个区域的能力提供了有价值的集成电路设计的自由度。 使用常规技术将集成电路芯片上的双极晶体管加工成发射点形成点。 但是，在发射极形成之前，将使用反应离子蚀刻干法蚀刻作为具有非常窄的基极晶体管的选定区域的发射极的基极区域。 将其中具有发射极开口的现有氮化硅/二氧化硅层用作该反应离子蚀刻程序的蚀刻掩模。 一旦蚀刻完成到期望的深度，则恢复正常处理以形成发射器和金属化的其余部分。

公开(公告)号：US4426655A

公开(公告)日：1984-01-17

申请号：US293413

申请日：1981-08-14

申请人： Harsaran S. Bhatia ,  David B. Eardley ,  Santosh P. Gaur

发明人： Harsaran S. Bhatia ,  David B. Eardley ,  Santosh P. Gaur

IPC分类号： G11C11/34 ,  H01L27/102 ,  H01L29/74 ,  H01L29/48

CPC分类号： H01L27/1028 ,  G11C11/34

摘要： A dynamic memory cell uses a low barrier Schottky contact at a drain region to eliminate the need for an external gating diode. The drain is separated from source and injector regions by a heavily doped N+ reach through region extending to a heavily doped N+ blanket semiconductor. Holes injected into one of the separated regions are trapped by high-low junctions and are detected by sensing the source-drain current.

摘要翻译： 动态存储单元在漏极区域使用低阻挡肖特基接触以消除对外部门控二极管的需要。 漏极通过重掺杂N +到达区域延伸到重掺杂的N +覆盖半导体与源极和注入器区域分离。 注入一个分离区域的孔被高低交点捕获，并通过感测源极 - 漏极电流来检测。

公开(公告)号：US08468337B2

公开(公告)日：2013-06-18

申请号：US10790966

申请日：2004-03-02

申请人： Santosh P. Gaur ,  William Eric Hall

发明人： Santosh P. Gaur ,  William Eric Hall

IPC分类号： H04L29/06

CPC分类号： H04L9/0844 ,  H04L49/9036 ,  H04L63/164

摘要： A system and method are described for secure data transfer over a network. According to an exemplary embodiment a system for secure data transfer over a network includes memory and a memory controller configured to transfer data received from the network to the memory. The system includes a processor, having logic configured to retrieve a portion of the data from the memory using the memory controller. The processor also includes logic configured to perform security operations on the retrieved portion of the data, and logic configured to store the operated-on portion of the data in the memory using the memory controller. The memory controller is further configured to transfer the operated-on portion of the data from the memory to the network.

摘要翻译： 描述了通过网络进行安全数据传输的系统和方法。 根据示例性实施例，用于通过网络进行安全数据传输的系统包括存储器和被配置为将从网络接收的数据传送到存储器的存储器控​​制器。 该系统包括处理器，其具有被配置为使用存储器控制器从存储器检索数据的一部分的逻辑。 处理器还包括被配置为对所检索的数据部分执行安全操作的逻辑，以及被配置为使用存储器控制器将数据的被操作部分存储在存储器中的逻辑。 存储器控制器还被配置为将数据的被操作部分从存储器传送到网络。

公开(公告)号：US07564976B2

公开(公告)日：2009-07-21

申请号：US10791415

申请日：2004-03-02

申请人： Santosh P. Gaur ,  William Eric Hall

发明人： Santosh P. Gaur ,  William Eric Hall

IPC分类号： H04L9/00 ,  H04L9/32 ,  G06F15/16 ,  G06F15/76

CPC分类号： H04L9/00 ,  G06F9/3879 ,  G06F21/72 ,  H04L2209/125

摘要： A system and method are described for performing security operations on network data. According to an exemplary embodiment, a system for performing security operations on network data includes memory and a data coprocessor configured to transfer data into and out of the memory. A plurality of processors are coupled to the memory and to the data coprocessor. Each processor is configured to perform, in parallel to one another, security operations on a portion of the data. The system includes a plurality of security coprocessors coupled to the memory. Each security coprocessor is coupled to a respective one of the processors and configured to assist the respective processor in performing security operations on the portion of the data.

摘要翻译： 描述了一种用于对网络数据执行安全操作的系统和方法。 根据示例性实施例，用于对网络数据执行安全操作的系统包括存储器和被配置为将数据传入和传出存储器的数据协处理器。 多个处理器耦合到存储器和数据协处理器。 每个处理器被配置为彼此并行地执行对一部分数据的安全操作。 该系统包括耦合到存储器的多个安全协处理器。 每个安全协处理器耦合到相应的一个处理器，并且被配置为帮助相应的处理器对数据的该部分执行安全操作。

公开(公告)号：US4435898A

公开(公告)日：1984-03-13

申请号：US360731

申请日：1982-03-22

申请人： Santosh P. Gaur ,  John S. Lechaton ,  Gurumakonda R. Srinivasan

发明人： Santosh P. Gaur ,  John S. Lechaton ,  Gurumakonda R. Srinivasan

IPC分类号： H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L21/302 ,  H01L21/22

CPC分类号： H01L29/1004 ,  H01L21/3065 ,  H01L29/7325

摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The bipolar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitter is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter is etched. and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth. The transistor characteristics depend strongly upon the base width so the etching is controlled to very tight dimensions.

摘要翻译： 描述了允许制造非常窄的基极宽度双极晶体管的工艺。 选择性地改变晶体管特性的能力为集成电路的设计提供了一定程度的自由度。 使用常规技术将双极晶体管加工直到发射体形成点。 但是，在发射极形成之前，使用反应离子蚀刻干法蚀刻作为发射极的基极区域。 将其中具有发射极开口的现有氮化硅/二氧化硅层用作该反应离子蚀刻程序的蚀刻掩模。 一旦蚀刻完成到期望的深度，则恢复正常处理以形成发射器和金属化的其余部分。 因为发射极下的本征基底被蚀刻。 并且之后形成正常发射体，蚀刻将基底宽度减小近似等于蚀刻深度的量。 晶体管特性强烈依赖于基极宽度，因此蚀刻被控制到非常紧密的尺寸。