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9 条记录 (耗时 0.015 秒)

    Duty ratio correction circuit
    1.
    发明授权
    Duty ratio correction circuit 有权
    占空比校正电路

    公开(公告)号：US08471616B2

    公开(公告)日：2013-06-25

    申请号：US13533001

    申请日：2012-06-26

    申请人： Young-wook Kim ,  Soon-bok Jang ,  Jong-uk Song ,  Hwa-seok Oh ,  Sung-ha Kim

    发明人： Young-wook Kim ,  Soon-bok Jang ,  Jong-uk Song ,  Hwa-seok Oh ,  Sung-ha Kim

    IPC分类号： H03L7/06

    CPC分类号： H03K5/1565

    摘要： A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that is connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.

    摘要翻译： 一种用于校正时钟信号的占空比的占空比校正电路。 占空比校正电路包括不对称缓冲器，其接收时钟信号并根据控制信号调整时钟信号的占空比; 时钟发生电路，连接到不对称缓冲器并检测时钟信号的占空比; 以及根据时钟信号的占空比产生控制信号的控制器。 将控制器的操作作为程序记录在计算机可读记录介质上。

    MEMORY SYSTEM AND DATA PROCESSING METHOD THEREOF
    2.
    发明申请
    MEMORY SYSTEM AND DATA PROCESSING METHOD THEREOF 有权
    存储器系统及其数据处理方法

    公开(公告)号：US20100064200A1

    公开(公告)日：2010-03-11

    申请号：US12512097

    申请日：2009-07-30

    申请人： JinHyeok Choi ,  Hwaseok Oh ,  Jong-uk Song

    发明人： JinHyeok Choi ,  Hwaseok Oh ,  Jong-uk Song

    IPC分类号： G06F11/10 ,  G06F12/14

    CPC分类号： G11C16/26 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5646

    摘要： A data processing method of a memory system including a flash memory, which includes judging whether data initially read from a selected page of the flash memory is correctable. If the initially read data is judged not to be correctable, the data is newly read from the selected page based upon each of newly determined read voltages. Thereafter, error-free sub-sectors of the newly read data are collected based upon EDC data corresponding to the initially read data. The data of the error-free sub-sectors are then corrected based upon ECC data corresponding to the initially read data.

    摘要翻译： 一种包括闪速存储器的存储器系统的数据处理方法，其包括判断最初从闪速存储器的选定页面读取的数据是否可校正。 如果初始读取的数据被判定为不可校正，则基于每个新确定的读取电压从所选择的页面重新读取数据。 此后，基于与初始读取的数据相对应的EDC数据来收集新读取的数据的无差错子扇区。 然后，基于与初始读取的数据相对应的ECC数据来校正无差错子扇区的数据。

    VOLTAGE SCALING DEVICE OF SEMICONDUCTOR MEMORY
    3.
    发明申请
    VOLTAGE SCALING DEVICE OF SEMICONDUCTOR MEMORY 审中-公开
    半导体存储器的电压调节装置

    公开(公告)号：US20130094312A1

    公开(公告)日：2013-04-18

    申请号：US13584849

    申请日：2012-08-14

    申请人： SOON-BOK JANG ,  JONG-UK SONG ,  YOUNG-WOOK KIM ,  HWA-SEOK OH

    发明人： SOON-BOK JANG ,  JONG-UK SONG ,  YOUNG-WOOK KIM ,  HWA-SEOK OH

    IPC分类号： G11C7/00 ,  H01L35/00

    CPC分类号： G11C29/021 ,  G11C7/04 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/5002

    摘要： A voltage scaling device of a semiconductor memory device, the voltage scaling device including: a delay tester for determining the number of delay cells of a delay locked loop (DLL) required to cumulatively delay a clock signal having a constant frequency, and which is input to the DLL, by one clock period; a temperature sensor for measuring the temperature of the semiconductor memory device; and a voltage regulator for regulating a supply voltage of a voltage source which provides a chip voltage to the semiconductor memory device in response to the temperature measured by the temperature sensor and a locking value corresponding to the number of delay cells calculated by the delay tester.

    摘要翻译： 一种半导体存储器件的电压调节装置，所述电压缩放装置包括：延迟测试器，用于确定累积地延迟具有恒定频率的时钟信号所需的延迟锁定环（DLL）的延迟单元数量，并且其被输入 到DLL，一个时钟周期; 温度传感器，用于测量半导体存储器件的温度; 以及电压调节器，用于响应于由温度传感器测量的温度和对应于由延迟测试器计算的延迟单元的数量的锁定值，调节向半导体存储器件提供芯片电压的电压源的电源电压。

    Memory system and data processing method thereof
    5.
    发明授权
    Memory system and data processing method thereof 有权
    存储系统及其数据处理方法

    公开(公告)号：US08230303B2

    公开(公告)日：2012-07-24

    申请号：US12512097

    申请日：2009-07-30

    申请人： Jin-Hyeok Choi ,  Hwaseok Oh ,  Jong-uk Song

    发明人： Jin-Hyeok Choi ,  Hwaseok Oh ,  Jong-uk Song

    IPC分类号： G11C29/00

    CPC分类号： G11C16/26 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5646

    摘要： A data processing method of a memory system including a flash memory, which includes judging whether data initially read from a selected page of the flash memory is correctable. If the initially read data is judged not to be correctable, the data is newly read from the selected page based upon each of newly determined read voltages. Thereafter, error-free sub-sectors of the newly read data are collected based upon EDC data corresponding to the initially read data. The data of the error-free sub-sectors are then corrected based upon ECC data corresponding to the initially read data.

    摘要翻译： 一种包括闪速存储器的存储器系统的数据处理方法，其包括判断从闪速存储器的选定页面开始读取的数据是否可校正。 如果初始读取的数据被判定为不可校正，则基于每个新确定的读取电压从所选择的页面重新读取数据。 此后，基于与初始读取的数据相对应的EDC数据来收集新读取的数据的无差错子扇区。 然后，基于与初始读取的数据相对应的ECC数据来校正无差错子扇区的数据。

    DUTY RATIO CORRECTION CIRCUIT
    7.
    发明申请
    DUTY RATIO CORRECTION CIRCUIT 有权
    占空比校正电路

    公开(公告)号：US20130015897A1

    公开(公告)日：2013-01-17

    申请号：US13533001

    申请日：2012-06-26

    申请人： Young-wook KIM ,  Soon-bok JANG ,  Jong-uk SONG ,  Hwa-seok OH ,  Sung-ha KIM

    发明人： Young-wook KIM ,  Soon-bok JANG ,  Jong-uk SONG ,  Hwa-seok OH ,  Sung-ha KIM

    IPC分类号： H03K3/017 ,  H03L7/08

    CPC分类号： H03K5/1565

    摘要： A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that i s connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.

    摘要翻译： 一种用于校正时钟信号的占空比的占空比校正电路。 占空比校正电路包括不对称缓冲器，其接收时钟信号并根据控制信号调整时钟信号的占空比; 时钟发生电路，其连接到不对称缓冲器并检测时钟信号的占空比; 以及根据时钟信号的占空比产生控制信号的控制器。 将控制器的操作作为程序记录在计算机可读记录介质上。

    Memory system and address allocating method of flash translation layer thereof
    9.
    发明申请
    Memory system and address allocating method of flash translation layer thereof 审中-公开
    闪存转换层的存储器系统和地址分配方法

    公开(公告)号：US20100217920A1

    公开(公告)日：2010-08-26

    申请号：US12654388

    申请日：2009-12-18

    申请人： Jong-uk Song

    发明人： Jong-uk Song

    IPC分类号： G06F12/02 ,  G06F12/00

    CPC分类号： G06F12/0246 ,  G06F11/1441 ,  G06F12/0804 ,  G06F2212/1032 ,  G06F2212/7202 ,  Y02D10/13

    摘要： The memory system includes a flash memory and a memory controller. The flash memory has at least two addresses with different program times. The memory controller is configured to control the flash memory. The memory controller is configured to assign an address corresponding to a shorter program time from among the at least two addresses for a write operation executed at interruption of a power supply to the flash memory. The assigned address is used to store data of the memory controller in the flash memory.

    摘要翻译： 存储器系统包括闪存和存储器控制器。 闪存具有至少两个具有不同编程时间的地址。 存储器控制器被配置为控制闪存。 所述存储器控制器被配置为从所述至少两个地址中分配对应于较短编程时间的地址，用于在向闪存供电中断时执行的写入操作。 分配的地址用于将存储器控制器的数据存储在闪存中。