Channel estimation method and apparatus
    1.
    发明授权
    Channel estimation method and apparatus 有权
    信道估计方法和装置

    公开(公告)号:US09083572B2

    公开(公告)日:2015-07-14

    申请号:US13291490

    申请日:2011-11-08

    IPC分类号: H04K1/10 H04L27/28 H04L25/02

    CPC分类号: H04L25/022 H04L25/0224

    摘要: A method and apparatus for estimating a channel efficiently though pilot subcarrier signal transformation and noise reduction in the mobile communication system are provided. The apparatus includes a time domain transformer for transforming received pilot subcarrier signals to time domain signals, a noise reducer for reducing noises of the time domain signals, a frequency domain transformer for transforming the noise-reduced time domain signals to frequency domain signals, and a final channel estimator for estimating channel values of data subcarriers received using the frequency domain signals. The channel estimation method and apparatus of improves performance with the reduction of computational complexity.

    摘要翻译: 提供了一种通过导频子载波信号变换和噪声降低来有效地估计信道的方法和装置。 该装置包括用于将接收到的导频子载波信号变换为时域信号的时域变换器,用于减少时域信号噪声的降噪器,用于将噪声降低的时域信号变换为频域信号的频域变换器,以及 用于估计使用频域信号接收的数据子载波的信道值的最终信道估计器。 信道估计方法和装置通过降低计算复杂度来提高性能。

    Thin film transistor, and method of manufacturing the same
    2.
    发明授权
    Thin film transistor, and method of manufacturing the same 有权
    薄膜晶体管及其制造方法

    公开(公告)号:US08952376B2

    公开(公告)日:2015-02-10

    申请号:US13049547

    申请日:2011-03-16

    摘要: A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a first gate electrode and an active layer including a crystalline oxide semiconductor which is insulated from the first gate electrode by a first insulating layer and the active layer is arranged to overlap the first gate electrode. A source electrode is formed including at least a portion overlaps the active layer, and a drain electrode is arranged being spaced apart from the source electrode and at least a portion of the drain electrode overlaps the active layer, wherein the source electrode and the drain electrode are insulated from the first gate electrode by the first insulating layer.

    摘要翻译: 提供薄膜晶体管及其制造方法。 薄膜晶体管包括第一栅电极和有源层,其包括通过第一绝缘层与第一栅电极绝缘的结晶氧化物半导体,并且有源层布置成与第一栅电极重叠。 源极电极形成为包括至少一部分与有源层重叠的部分,并且排列电极被布置成与源电极间隔开,并且漏电极的至少一部分与有源层重叠,其中源电极和漏电极 通过第一绝缘层与第一栅极绝缘。

    Thin film transistor array panel and method for manufacturing the same
    6.
    发明授权
    Thin film transistor array panel and method for manufacturing the same 失效
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号:US08252639B2

    公开(公告)日:2012-08-28

    申请号:US12951981

    申请日:2010-11-22

    IPC分类号: H01L21/00

    摘要: The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

    摘要翻译: 本发明提供一种薄膜晶体管阵列板,包括:绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层,形成在栅极线上; 形成在所述栅极绝缘层上且与所述栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

    THIN FILM TRANSISTOR ARRAY AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    THIN FILM TRANSISTOR ARRAY AND METHOD OF MANUFACTURING THE SAME 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号:US20120208330A1

    公开(公告)日:2012-08-16

    申请号:US13450643

    申请日:2012-04-19

    IPC分类号: H01L21/336

    摘要: A method of manufacturing a thin film transistor array substrate includes: forming a gate pattern on a substrate; forming a first gate insulating film and a second gate insulating film on the substrate; forming a source/drain pattern and a semiconductor pattern on the substrate; forming a passivation film on the substrate; forming a photo-resist pattern on the passivation film; patterning the passivation film using the photo-resist pattern to form a passivation film pattern, the patterning of the passivation film including over-etching the passivation film to form an open region in the passivation film; forming a transparent electrode film on the substrate; removing the photo-resist pattern and a portion of the transparent electrode film on the photo-resist pattern; and forming a pixel electrode on the first gate insulating layer.

    摘要翻译: 制造薄膜晶体管阵列基板的方法包括:在基板上形成栅极图案; 在所述基板上形成第一栅极绝缘膜和第二栅极绝缘膜; 在衬底上形成源极/漏极图案和半导体图案; 在衬底上形成钝化膜; 在钝化膜上形成光刻胶图案; 使用光刻胶图形图案化钝化膜以形成钝化膜图案,钝化膜的图案化包括过蚀刻钝化膜以在钝化膜中形成开放区域; 在基板上形成透明电极膜; 在所述光刻胶图案上除去所述光刻胶图案和所述透明电极膜的一部分; 以及在所述第一栅极绝缘层上形成像素电极。

    THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    薄膜晶体管基板及其制造方法

    公开(公告)号:US20120091461A1

    公开(公告)日:2012-04-19

    申请号:US13219379

    申请日:2011-08-26

    IPC分类号: H01L29/786 H01L21/336

    摘要: A thin film transistor display substrate and a method of manufacturing the same are provided. The thin film transistor substrate includes a gate electrode formed on a display substrate, an active layer formed on the gate electrode to overlap with the gate electrode and including polycrystalline silicon, a first ohmic contact layer formed on the active layer, a second ohmic contact layer formed on the first ohmic contact layer, and a source electrode and a drain electrode each formed on the second ohmic contact layer.

    摘要翻译: 提供薄膜晶体管显示基板及其制造方法。 薄膜晶体管基板包括形成在显示基板上的栅电极,形成在栅电极上以与栅电极重叠并包括多晶硅的有源层,形成在有源层上的第一欧姆接触层,第二欧姆接触层 形成在第一欧姆接触层上,以及源电极和漏极,各自形成在第二欧姆接触层上。

    Display substrate and method of manufacturing the same
    9.
    发明授权
    Display substrate and method of manufacturing the same 有权
    显示基板及其制造方法

    公开(公告)号:US08008662B2

    公开(公告)日:2011-08-30

    申请号:US12626587

    申请日:2009-11-25

    IPC分类号: H01L29/04 H01L29/00 H01L31/00

    摘要: A display substrate having a low-resistance metallic layer and a method of manufacturing the display substrate. The gate conductors are extended in a first direction. The source conductors are extended in a second direction crossing the first direction including a lower layer of molybdenum or a molybdenum alloy, and an upper layer of aluminum or an aluminum alloy. The pixel areas are defined by the gate conductors and the source conductors. A switching element is formed in each of the pixel areas and includes a gate electrode extended from the gate conductor and a source electrode extended from the source conductor. The pixel electrode includes a transparent conductive material, and is electrically connected to a drain electrode of the switching element.

    摘要翻译: 具有低电阻金属层的显示基板和制造显示基板的方法。 栅极导体沿第一方向延伸。 源极导体在与第一方向交叉的第二方向上延伸,包括下层的钼或钼合金,以及铝或铝合金的上层。 像素区域由栅极导体和源极导体限定。 开关元件形成在每个像素区域中,并且包括从栅极导体延伸的栅电极和从源极延伸的源电极。 像素电极包括透明导电材料,并且电连接到开关元件的漏电极。

    Slotless motor
    10.
    发明授权
    Slotless motor 有权
    无槽电机

    公开(公告)号:US07990013B2

    公开(公告)日:2011-08-02

    申请号:US12321989

    申请日:2009-01-28

    IPC分类号: H02K1/06

    CPC分类号: H02K3/47

    摘要: A stator coil of a slotless motor is disclosed in which the stator coil is formed in such a manner that respective both distal ends of two unit coil bodies, each unit coil body arranged to face each other, are respectively coupled to form a plurality of circular coil bodies, each circular coil body having a different inner diameter, and a circular coil body having a smaller inner diameter is sequentially inserted into an inner side of a circular coil body having a larger inner diameter, whereby a horizontal width of the plurality of unit coil bodies of U, V and W phases is equal there among to cause the strength of the magnetic field of U, V and W phases to be equal, and to allow the stator to be accurately manufactured, thereby catering to a designer's intention and markedly simplifying the assembly processes.

    摘要翻译: 公开了一种无槽电动机的定子线圈,其中定子线圈以这样的方式形成:两个单元线圈体的相应的两个远端,每个单元线圈体分别彼此相对配置,以形成多个圆形 线圈体,具有不同内径的每个圆形线圈体和具有较小内径的圆形线圈体依次插入到具有较大内径的圆形线圈体的内侧,由此,多个单元的水平宽度 U,V,W相的线圈体相等,使U,V,W相的磁场强度相等,能够使定子精确制造,从而符合设计者的意图,明显地 简化装配过程。