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    PRESSURE-SENSITIVE ADHESIVE TAPE FOR PROTECTING ELECTRODE PLATE
    2.
    发明申请
    PRESSURE-SENSITIVE ADHESIVE TAPE FOR PROTECTING ELECTRODE PLATE 审中-公开
    用于保护电极板的压敏胶带

    公开(公告)号：US20120052295A1

    公开(公告)日：2012-03-01

    申请号：US13219792

    申请日：2011-08-29

    申请人： Jun IWATA ,  Mitsuru KAMITANI ,  Hiroomi HANAI

    发明人： Jun IWATA ,  Mitsuru KAMITANI ,  Hiroomi HANAI

    IPC分类号： B32B7/12

    CPC分类号： C09J7/38 ,  C09J2479/086 ,  Y10T428/28

    摘要： The present invention relates to a pressure-sensitive adhesive tape for protecting an electrode plate, containing: a substrate, and a pressure-sensitive adhesive layer provided on at least one side of a the substrate, in which the pressure-sensitive adhesive tape has a piercing resistance, obtained by the following calculation method, of 300 gf·mm or more; and has a heat shrinkage ratio, when heating is performed at 260° C. for 1 hour, of 1.0% or less in both of TD (width) direction and MD (length) direction, and in which the calculation method contains fixing the pressure-sensitive adhesive tape to a fixing plate in which a circular hole having a diameter of 11.28 mm is formed, piercing a needle of which the end of has a curvature radius of 0.5 mm to the pressure-sensitive adhesive tape at a speed of 2 mm/s under condition of 23±2° C., and measuring a maximum load (gf) and a maximum elongation (mm) of the pressure-sensitive adhesive tape when the needle penetrates the pressure-sensitive adhesive tape; and the piercing resistance is calculated by the following equation (1): Piercing resistance=[Maximum load (gf)]×[Maximum elongation (mm) of the pressure-sensitive adhesive tape]×½  (1).

    摘要翻译： 本发明涉及一种用于保护电极板的压敏粘合带，其包含：基材和设置在基材的至少一侧上的压敏粘合剂层，其中该粘合带具有 通过以下计算方法获得的穿孔电阻为300gf·mm以上; 并且在TD（宽度）方向和MD（长度）方向均为260℃，1小时以上1.0％以下的加热时，具有热收缩率，其中计算方法包括固定压力 形成有直径为11.28mm的圆形孔的固定板，将其曲率半径为0.5mm的端部的针以2mm的速度穿透到压敏粘合带 在23±2℃的条件下测量，并且当针穿透压敏粘合带时测量压敏粘合带的最大载荷（gf）和最大伸长率（mm）; 通过下式（1）计算穿刺阻力：穿刺阻力= [最大载荷（gf）]×[粘合带的最大伸长率（mm）]×½（1）。

    Viterbi decoding method and device thereof
    3.
    发明授权
    Viterbi decoding method and device thereof 失效
    维特比解码方法及其装置

    公开(公告)号：US06199191B1

    公开(公告)日：2001-03-06

    申请号：US09095761

    申请日：1998-06-11

    申请人： Jun Iwata

    发明人： Jun Iwata

    IPC分类号： H03M1341

    CPC分类号： H03M13/6508 ,  H03M13/4107 ,  H03M13/4169

    摘要： A Viterbi decoding method for decoding a received signal, doing an ACS process and a trace back process a first number of times, and doing the ACS process a second number of times and the trace back process the first number of times until the trace back process is complete for all of the bits to be decoded if the tracing back has not already been finished for all bits, the Viterbi decoding method further including: after the trace back processing has finished for all of the bits to be decoded, deciding a fame error based on the result of calculating a Hamming distance between the received signal and re-encoded decoded signal, and possibly changing the first number and/or the second number depending on value stored in a counter which signifies the condition of the frame error for the past several times.

    摘要翻译： 一种用于对接收到的信号进行解码，第一次进行ACS处理和追溯处理的维特比解码方法，并且进行第二次的ACS处理和第一次追溯处理，直到回溯处理 对于所有比特都完成，如果跟踪还没有完成所有比特，维特比解码方法还包括：在跟踪返回处理已经完成了要解码的所有比特之后，决定名望错误 基于计算接收信号和再编码解码信号之间的汉明距离的结果，并且可能根据存储在计数器中的值来改变第一数量和/或第二数量，该值表示过去的帧错误的条件 几次。

    Decoder with an error control adaptively applied on the basis of the estimated position of a slot in a frame
    4.
    发明授权
    Decoder with an error control adaptively applied on the basis of the estimated position of a slot in a frame 失效
    基于帧中的时隙的估计位置自适应地应用错误控制的解码器

    公开(公告)号：US5901160A

    公开(公告)日：1999-05-04

    申请号：US806615

    申请日：1997-02-26

    申请人： Masami Abe ,  Jun Iwata

    发明人： Masami Abe ,  Jun Iwata

    IPC分类号： H03M7/00 ,  H04B1/74 ,  H04L1/00 ,  H04L7/00 ,  H03M13/00

    CPC分类号： H04L1/0057 ,  H04L1/0009 ,  H04L1/0061

    摘要： A decoder which is adapted to receive a frame of coded data consisting of multiple slots including intra-frame position information indicating positions of the slots in the frame to decode the coded data, and which adaptively applies appropriate ones of plural error control methods depending on the position of the slots in the frame. An estimated value of the intra-frame position information of a current slot and a fixed amount of variation per slot of the intra-frame position information are generated in accordance with an estimated value of the intra-frame position information of an immediately preceding slot. Synchronization is established between a received value and the estimated value of the intra-frame position information. An error control method to be applied to the current slot in the synchronous state of the received value and the estimated value is determined in response to the estimated value of the intra-frame position information of the current slot generated. The decoder can achieve error control of received data correctly even if an error occurs with the received value of the intra-frame position information.

    摘要翻译： 一种解码器，适于接收由多个时隙组成的编码数据的帧，所述多个时隙包括指示帧中的时隙的位置的帧内位置信息以对编码数据进行解码，并且根据所述多个错误控制方法自适应地应用 插槽在框架中的位置。 根据前一时隙的帧内位置信息的估计值，生成当前时隙的帧内位置信息的估计值和帧内位置信息的时隙的固定变化量。 在接收值与帧内位置信息的估计值之间建立同步。 响应于所生成的当前时隙的帧内位置信息的估计值，确定应用于接收值的同步状态下的当前时隙的误差控制方法和估计值。 即使帧内位置信息的接收值发生错误，解码器也可以正确地实现接收到的数据的错误控制。

    Viterbi decoding method and viterbi decoding circuit
    5.
    发明授权
    Viterbi decoding method and viterbi decoding circuit 失效
    维特比解码方法和维特比解码电路

    公开(公告)号：US5887007A

    公开(公告)日：1999-03-23

    申请号：US799826

    申请日：1997-02-13

    申请人： Jun Iwata ,  Masami Abe

    发明人： Jun Iwata ,  Masami Abe

    IPC分类号： H03M13/23 ,  H03M13/41 ,  H04L1/00 ,  G06F11/10 ,  H03M13/12

    CPC分类号： H03M13/4161 ,  H03M13/4123 ,  H04L1/0054

    摘要： A convolutional code having identical initial and final states is decoded by using the Viterbi algorithm to trace a path starting from a first state and ending at a second state. If necessary, the trace is repeated, starting from the second state, provided the second state is not the same as the first state. The output result is then obtained from the second trace.

    摘要翻译： 具有相同初始状态和最终状态的卷积码通过使用维特比算法来解码，以跟踪从第一状态开始并以第二状态结束的路径。 如果需要，如果第二状态与第一状态不同，则从第二状态开始重复轨迹。 然后从第二个跟踪获得输出结果。

    Data processor executing microprograms according to a plurality of system architectures
    6.
    发明授权
    Data processor executing microprograms according to a plurality of system architectures 失效
    数据处理器根据多个系统架构执行微程序

    公开(公告)号：US4691278A

    公开(公告)日：1987-09-01

    申请号：US726440

    申请日：1985-04-23

    申请人： Jun Iwata

    发明人： Jun Iwata

    IPC分类号： G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/22

    CPC分类号： G06F9/30145 ,  G06F9/268 ,  G06F9/3017

    摘要： A data processor controlled by microprograms which can run a desired program in a selected one of multiple system architectural modes. In the data processor, the operation code of the instruction is used as an address for a decoding information storage which stores a plurality of pairs of a microinstruction start address and an editing format control word. A selector selects a pair of a start microinstruction address and an editing format control word. The microinstruction start address is used for accessing a microcode control storage storing a plurality of microprograms in microinstruction form. The editing format control is used as an editing designation signal for editing the operand of the instruction according to the selected mode.

    摘要翻译： 由微程序控制的数据处理器，其可以在多个系统架构模式中选定的一个运行所需程序。 在数据处理器中，指令的操作码用作存储多对微指令开始地址和编辑格式控制字的解码信息存储器的地址。 选择器选择一对起始微指令地址和编辑格式控制字。 微指令开始地址用于访问以微指令形式存储多个微程序的微代码控制存储器。 编辑格式控制用作编辑指定信号，用于根据所选择的模式编辑指令的操作数。

    OXADIAZOLE COMPOUND AND FUNGICIDE FOR AGRICULTURAL AND HORTICULTURAL USE
    7.
    发明申请
    OXADIAZOLE COMPOUND AND FUNGICIDE FOR AGRICULTURAL AND HORTICULTURAL USE 有权

    公开(公告)号：US20210403461A1

    公开(公告)日：2021-12-30

    申请号：US16625320

    申请日：2018-07-24

    申请人： Jun IWATA ,  Yuka NAKAMURA ,  Tsukiho HAYASHI ,  Shinya WATANABE ,  HIroshi SANO

    发明人： Jun IWATA ,  Yuka NAKAMURA ,  Tsukiho HAYASHI ,  Shinya WATANABE ,  HIroshi SANO

    IPC分类号： C07D413/10 ,  A01N43/82 ,  C07D413/14 ,  A01N43/90 ,  C07D471/04

    摘要： This fungicide for agricultural and horticultural use includes a compound represented by formula (I) (in the formula, X represents a halogen group, or the like; n represents any integer of 0 to 4; when n is 2 or more, X may be the same or different; L represents a single bond or a substituted or unsubstituted C1-6 alkylene group; Q is a group represented by formula (Q-1) or formula (Q-2) (in the formulae, * represents a binding site; Y1 is N or CR1; Y2 is N or CR2; Y3 is N or CR3; Y4 is N or CR4, at least two of Y1 to Y4 are not nitrogen atoms; R1, R2, R3, and R4, each independently represent a hydrogen atom, a substituted or unsubstituted C1-6 alkyl group, or the like; R represents a substituted or unsubstituted C1-6 alkyl group or the like; G represents a substituted or unsubstituted C1-6 alkylene group; T represents a substituted or unsubstituted C1-6 alkylene group; Y5 is N or CH)) or a salt thereof.

    Real-time convolutional decoder with block synchronizing function
    9.
    发明授权
    Real-time convolutional decoder with block synchronizing function 失效
    具有块同步功能的实时卷积解码器

    公开(公告)号：US5422894A

    公开(公告)日：1995-06-06

    申请号：US267593

    申请日：1994-06-21

    申请人： Masami Abe ,  Jun Iwata

    发明人： Masami Abe ,  Jun Iwata

    IPC分类号： H04L1/00 ,  H03M13/23 ,  H03M13/33 ,  H03M13/41 ,  H04L7/04 ,  H04L25/08 ,  H03M13/12

    CPC分类号： H04L7/048 ,  H03M13/33 ,  H03M13/41

    摘要： A decoder receives frames of data that have been block coded, then convolutionally coded, at a rate of multiple frames per block. As each frame is received, the decoder counts it, stores convolutional code path information, and updates metric values pertaining to the paths. Once per block of frames, the decoder selects a path having the best metric value, convolutionally decodes one block, detects errors from both the block code and path metric, and generates error information. From the error information, the decoder decides whether block synchronization has been acquired or lost, and clears, decrements, or sets the frame count accordingly. If synchronized, the decoder outputs the block and its error information, and updates the path memory in preparation to decode the next block. Otherwise, the decoder prepares to reacquire block synchronization.

    摘要翻译： 解码器以每块多个帧的速率接收已被块编码的数据帧，然后进行卷积编码。 当每个帧被接收时，解码器对其进行计数，存储卷积码路径信息，并更新与路径有关的度量值。 每块帧一次，解码器选择具有最佳度量值的路径，对一个块进行卷积解码，从块码和路径度量中检测错误，并产生错误信息。 从错误信息中，解码器判定是否获取或丢失块同步，并相应地清除，减少或设置帧计数。 如果同步，解码器输出块及其错误信息，并准备更新路径存储器以解码下一个块。 否则，解码器准备重新获取块同步。

    System for independently controlling supply of a clock signal to a selected group of the arithmetic processors connected in series
    10.
    发明授权
    System for independently controlling supply of a clock signal to a selected group of the arithmetic processors connected in series 失效
    用于独立控制时钟信号供应给系列连接的算术处理器的选定系统

    公开(公告)号：US5230046A

    公开(公告)日：1993-07-20

    申请号：US419274

    申请日：1989-10-10

    申请人： Jun Iwata ,  Hiroyuki Kasai

    发明人： Jun Iwata ,  Hiroyuki Kasai

    IPC分类号： G06F15/16 ,  G06F1/04 ,  G06F1/10 ,  G06F11/00 ,  G06F11/07 ,  G06F11/20 ,  G06F15/177 ,  G06F15/80

    CPC分类号： G06F11/0724 ,  G06F1/10 ,  G06F11/0793 ,  G06F15/8007 ,  G06F11/2043

    摘要： In a computer system comprising first through K-th arithmetic processors connected to a control section (18) in an ascending order, where K represents a positive integer which is not less than two, a memorizing unit (20) memorizes first and second information. A clock controlling unit (21) detects a fault signal produced by a k-th arithmetic processor, where k represents one of 1 through K. When the memorizing unit memorizes the first information, the controlling unit controls a supplying unit (19) to put the k-th through the K-th arithmetic processors out of operation. When the memorizing unit memorizes the second information, the controlling unit controls the supplying unit to put the first through the K-th arithmetic processors out of operation even upon production of the fault signal by any one of the first through the K-th arithmetic processors. Besides a first group of the first through the K-th arithmetic processors, a second group may be included in the computer system to comprise an additional arithmetic processor connected to the control section. When the memorizing unit memorizes the first information, the additional arithmetic processor is kept in operation. When the memorizing unit memorizes the second information, the additional arithmetic processor is put out of operation.