Method of fabricating copper damascene and dual damascene interconnect wiring
    4.
    发明授权
    Method of fabricating copper damascene and dual damascene interconnect wiring 失效
    铜镶嵌和双镶嵌互连布线的制作方法

    公开(公告)号:US07176119B2

    公开(公告)日:2007-02-13

    申请号:US10711456

    申请日:2004-09-20

    IPC分类号: H01L21/4763

    摘要: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.

    摘要翻译: 一种集成电路和集成电路的制造方法,所述方法包括:(a)提供衬底; (b)在所述基板上形成铜扩散阻挡层; (c)在铜扩散阻挡层的顶表面上形成电介质层; (d)在所述电介质层中形成铜镶嵌或双镶嵌线,所述铜镶嵌件的顶表面或与所述电介质层的顶表面共面的双镶嵌线; (e)在所述导线的顶表面和所述电介质层的顶表面上形成第一覆盖层; (f)在步骤(e)执行与所述集成电路相关的一个或多个表征程序之后; 和(g)在步骤(e)之后,在第一覆盖层的顶表面上形成第二覆盖层。